Contents-14
Chapter 16
External Interrupt Functions
16.1 Overview ........................................................................................................ 16-1
16.2 External Interrupt Registers ........................................................................... 16-1
16.2.1 Description of External Interrupt Registers ............................................... 16-2
(1) External interrupt control register 0 (EXI0CON) ....................................... 16-2
(2) External interrupt control register 1 (EXI1CON) ....................................... 16-3
(3) External interrupt control register 2 (EXI2CON) ....................................... 16-4
16.2.2 Example of External Interrupt-related Register Settings ........................... 16-5
(1) Port 6 mode register (P6IO) ...................................................................... 16-5
(2) Port 9 mode register (P9IO) ...................................................................... 16-5
(3) Port 6 secondary function control register (P6SF) .................................... 16-5
(4) Port 9 secondary function control register (P9SF) .................................... 16-5
(5) External interrupt control register 0 (EXI0CON) ....................................... 16-5
(6) External interrupt control register 1 (EXI1CON) ....................................... 16-5
(7) External interrupt control register 2 (EXI2CON) ....................................... 16-5
16.3 EXINT0 to EXINT7 Interrupts ......................................................................... 16-6
Chapter 17
Interrupt Processing Functions
17.1 Overview ........................................................................................................ 17-1
17.2 Interrupt Function Registers ........................................................................... 17-2
17.3 Description of Interrupt Processing ................................................................ 17-3
17.3.1 Non-Maskable Interrupt (NMI) .................................................................. 17-3
17.3.2 Maskable Interrupts .................................................................................. 17-5
(1) Interrupt request registers (IRQ0 to IRQ4) ............................................... 17-5
(2) Interrupt enable registers (IE0 to IE4) ....................................................... 17-5
(3) Master interrupt enable flag (MIE) ............................................................ 17-5
(4) Master interrupt priority flag (MIPF) .......................................................... 17-5
(5) Interrupt priority control registers (IP0 to IP9) ........................................... 17-6
17.3.3 Priority Control of Maskable Interrupts ................................................... 17-10
(1) Basic interrupt control ............................................................................. 17-10
(2) Multiple interrupt control ......................................................................... 17-10
17.4 IRQ, IE and IP Register Configurations for Each Interrupt .......................... 17-12
17.4.1 Interrupt Request Registers (IRQ0 to IRQ4) ........................................... 17-12
(1) Interrupt request register 0 (IRQ0) .......................................................... 17-12
(2) Interrupt request register 1 (IRQ1) .......................................................... 17-13
(3) Interrupt request register 2 (IRQ2) .......................................................... 17-14
(4) Interrupt request register 3 (IRQ3) .......................................................... 17-15
(5) Interrupt request register 4 (IRQ4) .......................................................... 17-16
17.4.2 Interrupt Enable Registers (IE0 to IE4) ................................................... 17-17
(1) Interrupt enable register 0 (IE0) .............................................................. 17-17