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參數(shù)資料
| 型號： | MSM7540L |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | Single Rail ADPCM CODEC |
| 中文描述： | 單軌差分PcM編解碼器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MSM7540L |
5/15
MSM7540L/7560L
Semiconductor
SG
Analog signal ground voltage output.
The output voltage of this pin is approximately 1.4 V. Put bypass capacitors between this pin
and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if
necessary, should be used via a buffer.
AG
Analog ground.
DG
Digital ground.
This ground is separated internally from the analog signal ground pin (AG). The DG pin must
be kept as close as possible to AG on the PCB.
V
DD
+3 V power supply.
LPS
PCM coding law selection.
MSM7540L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
MSM7560L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
m
-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
PDN
Power down control input.
If this pin is "0", this device is in the power-down state.
Normally, this pin is set to "1".
RES
Optional reset input specified by ITU-T Recommendation G. 721.
If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125
m
s or
more.
MCK
Master clock input.
The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA,
BCLKB, XSYNC, and RSYNC.
PCMSO
Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.
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| MSM7540LG3-K | 制造商:ROHM Semiconductor 功能描述: |
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| MSM7541 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:Single Rail CODEC |
| MSM7542 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:Single Rail CODEC |
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