參數(shù)資料
型號: MSM7580
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: ITU-T G.721 ADPCM TRANSCODER
中文描述: ITU - T的G.721差分PcM碼器
文件頁數(shù): 11/18頁
文件大小: 207K
代理商: MSM7580
11/17
Semiconductor
MSM7580
THR Processing Timing
Timing Block Diagrams, when CODER and DECODER output data, are shown in the following
figures.
The parallel to serial conversion of the output unit employs a load format and the load point is
at the rising edge of a synchronous signal.
Therefore, input THR signal with respect to SYNCA for CODER with timing of satisfying ts and
th conditions shown in the figure.
For DECODER, THR signal should be input even when through-data is input.
The input timing should satisfy the conditions shown in the following figures.
CODER
8
Through-data
4b
ADPCM
CODER
8b
S
E
L
SYNCA
SOA
BCLKA
Serial
Parallel
SYNCP
SIP
BCLKP
THR
Latch timing=A
MSB
LSB
th
ts
MSB
ts=100ns or more
th=100ns or more
PCM side SYNC (SYNCP)
PCM Input (SIP)
Internal Latch timing (A)
Internal Input Data
ADPCM side SYNC (SYNCA)
Through-data Output (SOA)
BCLKA
THR
Through-data
Parallel
Serial
Latch
Note:
That data-ship may occur when the rising edge (data load point) of SYNCA and input of
the internal latch timing overlap each other.
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