參數(shù)資料
型號(hào): MSM7580
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: ITU-T G.721 ADPCM TRANSCODER
中文描述: ITU - T的G.721差分PcM碼器
文件頁(yè)數(shù): 5/18頁(yè)
文件大小: 207K
代理商: MSM7580
5/17
Semiconductor
MSM7580
SYNCP1, SYNCP2
Synchronous signal input.
SYNCP1 and SYNCP2 control the PCM data input/output timing for Channel 1 (SIP1, SOP1)
and Channel 2 (SIP2, SOP2), respectively.
Since other synchronous signal input pins SYNCA1 and SYNCA 2 for ADPCM interfaces are also
provided, the PCM and ADPCM data can be input or output with different timing.
PCM and ADPCM data interfaces can be used at a mutually independent timing except same
timing.
Note:
When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Notes on Usage" should not be used.
BCLKP
Bit clock input.
This signal defines the PCM data transmission speed at the PCM data input/output pins.
BCLKP is used for Channels 1 and 2. Since BCLKA defines the data rate of the ADPCM data
interface, the PCM and ADPCM data can be input or output at different speeds.
LAW
PCM data companding law (A-law/
m
-law) selection.
Digital “1” and “0” correspond to A-law and
μ
-law, respectively.
PDN1
,
PDN2
Power down mode selection.
PDN1
and
PDN2
can be independently set to power down mode. When a digital “0” is applied,
these pins are in the power-down mode.
SIA1, SOA1
ADPCM serial data input (SIA1) and output (SOA1) pins for Channel 1.
SOA1 is an open-drain pin and enters to the high impedance state after outputting a continuous
4-bit serial data stream. When the data-through mode is selected, SOA1 enters to the high
impedance state after outputting an 8-bit serial data stream.
SIA2, SOA2
ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2.
These pins function the same as SIA1 and SOA1.
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