參數(shù)資料
型號： MSM7584C
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： π/4 Shift QPSK MODEM(π/4移動QPSK調(diào)制解調(diào)器/ADPCM編碼譯碼器)
中文描述： π/ 4移位的QPSK調(diào)制解調(diào)器（π/ 4移動的QPSK調(diào)制解調(diào)器/差分PcM編碼譯碼器）
文件頁數(shù)： 16/57頁
文件大?。?/td> 321K
代理商： MSM7584C
Semiconductor
MSM7584C
16/57
AFC/RCW
AFC operation and clock regeneration range specification signal input.
As shown in Figure 5, AFC information is reset when AFC/RCW and RPR go to "1" level. The
AFC operation starts after a certain time elapses.
The average number of AFC operation times is small when RPR is at "1" level.
The average number of AFC operation times is large when RPR is at "0" level.
If AFC/RCW is at "0" level, DPLL will not adjust the phase.
Figure 5 AFC Control Timing Diagram
AFC/RCW
AFC information
is reset.
RPR
Averag number of
AFC operation
times is small.
AFC information
is maintained.
AFC/RCW
RPR
AFC information
is maintained.
The clock generation circuit
starts with the previous
AFC information.
"0"
(CASE1)
(CASE2)
Average number of AFC
operation times is large.
Average number of AFC
operation times is large.
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