參數(shù)資料
型號(hào): MSM7602-001
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: Echo Canceler
中文描述: 回聲消除器
文件頁數(shù): 8/29頁
文件大?。?/td> 238K
代理商: MSM7602-001
Semiconductor
MSM7602
8/29
(4/5)
Pin
28-pin
SSOP
20
56-pin
QFP
34
Symbol
Type
Description
22
36
SYNCO
O
23
37
SCKO
O
24
38
RST
I
25
39
WDT
O
26
40
GC
I
Input signal by which the gain controller for the RIN input is
controlled and the RIN input level is controlled and howling is
prevented.
The gain controller adjusts the RIN input level when it is –20 dBm0 or
above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to
–20 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB.
Single Chip or Master Chip in a Cascade Connection
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.
Slave Chip in a Cascade Connection
Fixed at "L"
This pin is loaded in synchronization with the falling edge of the
INT
signal
or the rising edge of
RST
.
Test program end signal.
This signal is output when the one cycle (8kHz) of processing is completed.
Leave it open.
Reset signal.
"L": Reset mode
"H": Normal operation mode
Due to initialization, input signals are disabled for 100
m
s after reset
(after
RST
is returned from L to H).
Input the basic clock during the reset.
Output pins during the reset are in the following states :
High impedance: SOUT, ROUT, PD0 to 15
"L": WDT
"H":
OF1
,
OF2
Not affected: X2, SYNCO, SCKO,
IRLD
, MCKO
Transmit clock signal (256 kHz) for the PCM CODEC.
Connect to the SCK pin and the PCM CODEC transmit/receive clock pin.
Leave it open if using an external SCK.
8 kHz sync signal for the PCM CODEC.
Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin.
Leave it open if using an external SYNC.
PWDWN
I
Power-down mode control when powered down.
"L": Power-down mode
"H": Normal operation mode
During power-down mode, all input pins are disabled and output pins are
in the following states :
High impedance : SOUT, ROUT, PD0 to 15
"L": SYNCO, SCKO, MCKO
"H":
OF1
,
OF2
, X2
Holds the last state : WDT,
IRLD
Reset after the power-down mode is released.
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