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參數(shù)資料
| 型號(hào)： | MSM80C85AHRS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 355K |
| 代理商： | MSM80C85AHRS |
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5
Semiconductor
MSM80C85AHRS/GS/JS
Name
Address Branched To (1)
When Interrupt Occurs
Type Trigger
RST 7.5
3CH
34H
Rising edge (latched).
High level unitl sampled.
RST 6.5
RST 5.5
2CH
(2)
High level until sampled.
INTR
TRAP
Priority
2
3
4
5
1
24H
Rising edge and high level unit sampled.
Table 1 Interrupt Priority, Restart Address, and Sensitivity
Notes: (1) The processor pushes the PC on the stack before branching to the indicated
address.
(2) The address branched to depends on the instruction provided to the cpu
when the interrupt is acknowledged.
RESET IN
(Input)
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release
power down mode. The data and address buses and the control lines are 3-stated during RESET and
because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be
altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing
connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as
long as RESET IN is applied.
Symbol
Function
RESET OUT
(Output)
Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to
the processor clock and lasts an integral number of clock periods.
X1, X2
(Input)
X1 and X2 are connected to a crystal to drive the internal clock generator. X1 can also be an external
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal
operating frequency.
SID
(Input)
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
is executed.
SOD
(Output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
VCC
+ 5 Volt supply
GND
Ground Reference.
CLK
(Output)
Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM80C86A-10RS | 16-BIT, 10 MHz, MICROPROCESSOR, PDIP40 |
| MSM80C88A-10GS | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
| MSM80C88A-10RS | 8-BIT, 10 MHz, MICROPROCESSOR, PDIP40 |
| MSM80C88A-10JS | 8-BIT, 10 MHz, MICROPROCESSOR, PQCC44 |
| MSM80C88A-10GS-K | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM80C85ARS | 制造商:OK International 功能描述: 制造商:Panasonic Industrial Company 功能描述:IC |
| MSM80C86A-10GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:16-Bit CMOS MICROPROCESSOR |
| MSM80C86A-10JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:16-Bit CMOS MICROPROCESSOR |
| MSM80C86A-10RS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:16-Bit CMOS MICROPROCESSOR |
| MSM80C88A-10GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
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