參數(shù)資料
型號： MSM82C37B-5GS
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： PROGRAMMABLE DMA CONTROLLER
中文描述： 可編程DMA控制器
文件頁數(shù)： 13/34頁
文件大小： 301K
代理商： MSM82C37B-5GS
13/33
Semiconductor
MSM82C37B-5RS/GS/VJS
Symbol
EOP
Pin Name
End of Process
Input/Output
Input/Output
Function
EOP
is active-low bidirectional three-state signal. Unlike other
pins, this pin is an N-channel open drain. During DMA operations,
a low-level output pulse is obtained from this pin if the channel
word count changes from 0000H to FFFFH.
And DMA transfers can be terminated by pulling the
EOP
input to
low level. Both of these actions are called terminal count (TC).
When internal or external
EOP
is generated, the MSM82C37B-5
terminates the transfer and resets the DMA request.
When the EOP pin is not used, it is necessary to hold the pin at
high level by pull-up resistor to prevent the input of an EOP
by error. Also note that the
EOP
function cannot be satisfied in
cascade mode.
Hold Request
HRQ
Output
HRQ is active-high signal used as an output of hold request to
the CPU for system data bus control purposes. After HRQ has
become active, at least one clock cycle is required before HLDA
becomes active.
Address Enable
AEN
Output
AEN is active-high ouput signal used to indicate that output
signals sent from the MSM82C37B-5 to the system are valid.
And in addition to enabling external latch to hold the eight higher
order bits of the transfer address, this signal is also used to
disable other system bus buffers.
ADSTB is active-high signal used to strobe the eight higher order
bits of the transfer address by external latch.
DMA Acknowledge
0 - 3 Channels
DACK
0
-
DACK
3
Output
DACK is output signals used to indicate that DMA transfer to
peripheral devices has been permitted. (Available in each channel.)
Although these pins are switched to active-low when reset, they
can be programmed to become active-high.
Note that there is no DACK output signal during memory-memory
transfers.
Address 0 - 3
A
0
- A
3
Input/Output
A
0
- A
3
is bidirectional three-state signals used as input signals
for specifying the MSM82C37B-5 internal register to be accessed
by the CPU during idle cycles, and as an output the four lower
order bits of the transfer address during active cycles.
A
4
- A
7
is three-state signals used as an output the four higher
order bits of the transfer address during active cycles.
Address 4 - 7
A
4
- A
7
Output
Memory Read
MEMR
Output
MEMR
is active-low three-state output signal used as a control
signal in reading data from memory during read transfers and
memory-memory transfers.
MEMW
is active-low three-state output signal used as a control
signal in writing data into memory during write transfers and
memory-memory transfers.
Memory Write
MEMW
Output
Address Strobe
ADSTB
Output
PIN FUNCTIONS (continued)
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