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參數(shù)資料
| 型號： | MSM82C37B-5GS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大?。?/td> | 301K |
| 代理商： | MSM82C37B-5GS |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Cascade Transfer Mode
When DMA transfers involving more than four channels are required, connecting a multiple
number of MSM82C37A-5 devices in a cascade connection (see Figure 2 ) enables a simple
system extension. This mode is set by setting the first stage MSM82C37B-5 channel to cascade
mode. The DREQ and DACK lines for the first stage MSM82C37B-5 channel set to cascade mode
are connected to the HRQ and HLDA lines of the respective MSM82C37B-5 devices in the
second stage. The first stage MSM82C37B-5 DACK signal must be set to active-high, and the
DREQ signal to active-low.
Since the first stage MSM82C37B-5 is only used functionally in determining the order of priority
of each channel when cascade mode is set, only DREQ and DACK are used–all other inputs are
disregarded. And since the system may be hung up if the DMA transfer is activated by software
DREQ, do not set a software DREQ for channels where cascade mode has been set.
In addition to the dual stage cascade connection shown in Figure 2, triple stage cascade
connections are possible with the second stage also set to cascade mode.
CPU
HRQ
DREQ
DACK
HLDA
DREQ
DACK
HRQ
HLDA
DREQ
0 - 3
DACK
0 - 3
4
4
4
4
I/O
I/O
HRQ
HLDA
DREQ
0 - 3
DACK
0 - 3
Stage 1
MSM82C37B-5
Stage 2
MSM82C37B-5
Figure 2 MSM82C37B-5 Cascade Connection System
Autoinitialize Mode
Setting bit 4 of the mode register enables autoinitialization of that channel. Following TC
generation, autoinitialize involves writing of the base address and the base word count register
values in the respective current address and current word count registers. The same values as
in the current registers are written in the base registers by the CPU, and are not changed during
DMA transfers. When a channel has been set to autoinitialize, that channel may be used in a
second transfer without involving the CPU and without the mask bit being reset after the TC
generation.
Priority Modes
The MSM82C37B-5 makes use of two priority decision modes, and acknowledges the DMA
channel of highest priority among the DMA requesting channels.
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PDF描述 |
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| MSM82C43 | INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2JS | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2RS | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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