參數(shù)資料
型號(hào): MSM82C55A-2GS-2K
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: 24 I/O, PIA-GENERAL PURPOSE, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù): 3/27頁(yè)
文件大?。?/td> 207K
代理商: MSM82C55A-2GS-2K
10/26
Semiconductor
MSM82C55A-2RS/GS/VJS
BASIC FUNCTIONAL DESCRIPTION
Group A and Group B
When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each.
Group A: Port A (8 bits) and high order 4 bits of port C (PC7~PC4)
Group B:
Port B (8 bits) and low order 4 bits of port C (PC3~PC0)
Mode 0, 1, 2
There are 3 types of modes to be set by grouping as follows:
Mode 0: Basic input operation/output operation (Available for both groups A and B)
Mode 1: Strobe input operation/output operation (Available for both groups A and B)
Mode 2: Bidirectional bus operation (Available for group A only)
When used in mode 1 or mode 2, however, port C has bits to be defined as ports for control signal
for operation ports (port A for group A and port B for group B) of their respective groups.
Port A, B, C
The internal structure of 3 ports is as follows:
Port A: One 8-bit data output latch/buffer and one 8-bit data input latch
Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer
Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input)
Single bit set/reset function for port C
When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to
turn to low level) any one of 8 bits individually without affecting other bits.
相關(guān)PDF資料
PDF描述
MSM82C55A-2RS 24 I/O, PIA-GENERAL PURPOSE, PDIP40
MSM82C55A-2VJS 24 I/O, PIA-GENERAL PURPOSE, PQCC44
MSM82C59A-2GS-K 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32
MSM82C84A-2GS-K 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
MSM82C84A-2JS OTHER CLOCK GENERATOR, PQCC20
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