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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MSP430F4783IPZ |
| 寤犲晢锛� | Texas Instruments |
| 鏂囦欢闋佹暩(sh霉)锛� | 17/80闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MCU 16BIT 48KB FLASH 100LQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | The Ultra-Low Power MSP430 MSP430 Overview MSP430 Design Tools MSP430 Peripherals MSP430x2xx/4xx and Wireless Overview Portable Medical Solutions with MSP430 MSP430 for Utility Metering Solutions MSP430: How to JTAG MSP430, How To Use the Clock System Grace Software Graphical User Interface MCU Overview Driver Library MSP430Ware Overview |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | MSP430x4xx |
| 鏍稿績铏曠悊鍣細 | RISC |
| 鑺珨灏哄锛� | 16-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | I²C锛孖rDA锛孡IN锛孲CI锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 72 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 48KB锛�48K x 8 + 256B锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 2K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 3x16b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 100-LQFP |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | MSP-FET430U100-ND - KIT PROG/DEBUG MSP430F 100PIN PZ |
| 鍏跺畠鍚嶇ū锛� | 296-33434-5 MSP430F4783IPZ-ND |
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MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C MAY 2007 REVISED MARCH 2011
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage during program execution,
1.8
3.6
V
Supply voltage during program execution, SVS enabled, PORON = 1,
2.0
3.6
V
Supply voltage during program/erase flash memory,
2.2
3.6
V
Supply voltage, VSS
0
V
Operating free-air temperature range, TA
40
85
掳C
VCC = 1.8 V,
Duty Cycle = 50%
卤10%
dc
4.15
MHz
Processor frequency fSYSTEM (Maximum MCLK frequency)
VCC = 2.2 V,
Duty Cycle = 50%
卤10%
dc
7.5
MHz
Processor frequency fSYSTEM (Maximum MCLK frequency)
VCC = 2.7 V,
Duty Cycle = 50%
卤10%
dc
12
MHz
VCC 鈮� 3.3 V,
Duty Cycle = 50%
卤10%
dc
16
MHz
NOTES:
1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised abve minimum supply voltage plus the hysteresis of the SVS circuitry.
3. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
4. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this
datasheet.
4.15 MHz
12 MHz
16 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage V
Sys
tem
F
re
q
u
e
nc
y
M
H
z
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
7.5 MHz
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MS27656T17F99S | CONN RCPT 23POS WALL MNT W/SCKT |
| VI-J4B-IW-F3 | CONVERTER MOD DC/DC 95V 100W |
| VI-J4B-IW-F1 | CONVERTER MOD DC/DC 95V 100W |
| MS3116J14-19PW | CONN PLUG 19POS STRAIGHT W/PINS |
| AD9883AKSTZ-RL110 | IC INTERFACE FLAT 110MHZ 80LQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MSP430F4783IPZR | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 16B Ultra-Lo-Pwr MCU RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MSP430F4784IPZ | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 16B Ultra-Lo-Pwr MCU RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MSP430F4784IPZR | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 16B Ultra-Lo-Pwr MCU RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MSP430F478IPN | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 16B Ultra-Lo-Pwr MCU 48KB Fl 2KB RAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MSP430F478IPNR | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 16B Ultra-Lo-Pwr MCU 48KB Fl 2KB RAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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