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| 型號： | MSP430F5437IPNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封裝： | GREEN, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 51/99頁 |
| 文件大小： | 985K |
| 代理商： | MSP430F5437IPNR |
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MSP430F543x, MSP430F541x
www.ti.com
SLAS612C – AUGUST 2009 – REVISED MARCH 2010
USCI (UART Mode) - recommended operating conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fUSCI
USCI input clock frequency
External: UCLK
fSYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK
1
MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
2.2 V
50
600
tt
UART receive deglitch time(1)
ns
3 V
50
600
(1)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) - recommended operating conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50% ± 10%
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1), Figure 11 and Figure 12)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50% ± 10%
2.2 V
65
tSU,MI
SOMI input data setup time
ns
3 V
50
2.2 V
0
tHD,MI
SOMI input data hold time
ns
3 V
0
2.2 V
25
UCLK edge to SIMO valid,
tVALID,MO
SIMO output data valid time(2)
ns
CL = 20 pF
3 V
20
2.2 V
tHD,MO
SIMO output data hold time(3)
CL = 20 pF
ns
3 V
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 11 and Figure 12.
(3)
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 11 and Figure 12.
Copyright 2009–2010, Texas Instruments Incorporated
55
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