參數(shù)資料
型號(hào)： MSP430F5510IRGC
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
封裝： PLASTIC, VQFN-64
文件頁數(shù)： 62/99頁
文件大?。?/td> 1134K
代理商： MSP430F5510IRGC
PRODUCTPREVIEW
MSP430F550x
www.ti.com
SLAS645B – JULY 2009 – REVISED JULY 2010
10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
AVCC and DVCC are connected together,
AVCC
Analog supply voltage
AVSS and DVSS are connected together,
1.8
3.6
V
V(AVSS) = V(DVSS) = 0 V
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
V(Ax)
Analog input voltage range(2)
0
AVCC
V
P3.7 terminals
Operating supply current into
fADC10CLK = 5.0 MHz, ADC10ON = 1,
2.2 V
53
TBD
AVCC terminal. REF module
REFON = 0, SHT0 = 0, SHT1 = 0,
A
3 V
56
TBD
and reference buffer off.
ADC10DIV = 0, ADC10SREF = 00
Operating supply current into
fADC10CLK = 5.0 MHz, ADC10ON = 1,
AVCC terminal. REF module
REFON = 1, SHT0 = 0, SHT1 = 0,
3 V
162
TBD
A
on, reference buffer on.
ADC10DIV = 0, ADC10SREF = 01
fADC10CLK = 5.0 MHz, ADC10ON = 1,
IADC10_A
Operating supply current into
REFON = 0, SHT0 = 0, SHT1 = 0,
AVCC terminal. REF module
3 V
145
TBD
A
ADC10DIV = 0, ADC10SREF = 10,
off, reference buffer on.
VEREF = 2.5 V
fADC10CLK = 5.0 MHz, ADC10ON = 1,
Operating supply current into
REFON = 0, SHT0 = 0, SHT1 = 0,
AVCC terminal. REF module
3 V
114
TBD
A
ADC10DIV = 0, ADC10SREF = 11,
off, reference buffer off.
VEREF = 2.5 V
Only one terminal Ax can be selected at one
CI
Input capacitance
time from the pad to the ADC10_A capacitor
2.2 V
3.5
pF
array including wiring and pad.
AVCC > 2.0V, 0 V ≤ VAx ≤ AVCC
36
RI
Input MUX ON resistance
k
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC
96
(1)
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2)
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ().
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A linearity
fADC10CLK
2.2 V/3 V
0.45
5
5.5
MHz
parameters
Internal ADC10_A
fADC10OSC
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V/3 V
4
4.5
5
MHz
oscillator(1)
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
2.2 V/3 V
2.4
3.0
fADC10OSC = 4 MHz to 5 MHz
tCONVERT
Conversion time
s
External fADC10CLK from ACLK, MCLK or SMCLK,
(2)
ADC10SSEL
≠ 0
Turn on settling time of
tADC10ON
See (3)
100
ns
the ADC
1.8 V
1.5
s
tSample
Sampling time
RS = 1000 , RI = 36000 , CI = 3.5 pF
(4)
3.0 V
2.0
s
(1)
The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2)
12 × ADC10DIV × 1/fADC10CLK
(3)
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(4)
Approximately eight Tau (t) are needed to get an error of less than ±0.5 LSB
Copyright 2009–2010, Texas Instruments Incorporated
65
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