參數(shù)資料
型號: MSP430F5514IRGC
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
封裝: GREEN ,PLASTIC, VQFN-64
文件頁數(shù): 23/115頁
文件大?。?/td> 1159K
代理商: MSP430F5514IRGC
MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
PN
RGC
ZQE
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
P7.4/TB0.2
57
N/A
I/O
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
P7.5/TB0.3
58
N/A
I/O
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
P7.6/TB0.4
59
N/A
I/O
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 clock signal TBCLK input (not available on '5528, '5526, '5524, '5522,
P7.7/TB0CLK/MCLK
60
N/A
I/O
'5514, '5513 devices)
MCLK output (not available on '5528, '5526, '5524, '5522, '5514, '5513
devices)
B8,
VSSU
61
49
USB PHY ground supply
B9
General-purpose digital I/O - controlled by USB control register
PU.0/DP
62
50
A9
I/O
USB data terminal DP
PUR
63
51
B7
I/O
USB pullup resistor pin (open drain)
General-purpose digital I/O - controlled by USB control register
PU.1/DM
64
52
A8
I/O
USB data terminal DM
VBUS
65
53
A7
USB LDO input (connect to USB power source)
VUSB
66
54
A6
USB LDO output
V18
67
55
B6
USB regulated power (internal usage only, no external current loading)
AVSS2
68
56
A5
Analog ground supply
General-purpose digital I/O
P5.2/XT2IN
69
57
B5
I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
P5.3/XT2OUT
70
58
B4
I/O
Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation.
TEST/SBWTCK(3)
71
59
A4
I
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
PJ.0/TDO(4)
72
60
C5
I/O
JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK(4)
73
61
C4
I/O
JTAG test data input or test clock input
General-purpose digital I/O
PJ.2/TMS(4)
74
62
A3
I/O
JTAG test mode select
General-purpose digital I/O
PJ.3/TCK(4)
75
63
B3
I/O
JTAG test clock
Reset input active low
RST/NMI/SBWTDIO(3)
76
64
A2
I/O
Non-maskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
General-purpose digital I/O
P6.0/CB0/A0
77
1
A1
I/O
Comparator_B input CB0
Analog input A0 – ADC (not available on '551x devices)
General-purpose digital I/O
P6.1/CB1/A1
78
2
B2
I/O
Comparator_B input CB1
Analog input A1 – ADC (not available on '551x devices)
(3)
Please refer to Bootstrap Loader (BSL) and JTAG Operation for usage with BSL and JTAG functions
(4)
Please refer to JTAG Operation for usage with JTAG function.
Copyright 2009–2010, Texas Instruments Incorporated
15
相關(guān)PDF資料
PDF描述
MSP430F5528IRGC 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
MSP430F5522IRGC 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
MSP430F5524IRGC 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
MSP430F5526IRGC 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
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