參數(shù)資料
型號: MSP430F6631IZQW
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PBGA113
封裝: PLASTIC, BGA-113
文件頁數(shù): 17/105頁
文件大小: 1077K
代理商: MSP430F6631IZQW
PRODUCTPREVIEW
MSP430F663x
www.ti.com
SLAS566A – JUNE 2010 – REVISED JULY 2010
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.
Table 7. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT
-
Comparator_B output
1
PM_TB0CLK
Timer TB0 clock input
-
PM_ADC12CLK
-
ADC12CLK
2
PM_DMAE0
DMAE0 Input
-
PM_SVMOUT
-
SVM output
3
Timer TB0 high impedance input
PM_TB0OUTH
-
TB0OUTH
4
PM_TB0CCR0B
Timer TB0 CCR0 capture input CCI0B
Timer TB0: TB0.0 compare output Out0
5
PM_TB0CCR1B
Timer TB0 CCR1 capture input CCI1B
Timer TB0: TB0.1 compare output Out1
6
PM_TB0CCR2B
Timer TB0 CCR2 capture input CCI2B
Timer TB0: TB0.2 compare output Out2
7
PM_TB0CCR3B
Timer TB0 CCR3 capture input CCI3B
Timer TB0: TB0.3 compare output Out3
8
PM_TB0CCR4B
Timer TB0 CCR4 capture input CCI4B
Timer TB0: TB0.4 compare output Out4
9
PM_TB0CCR5B
Timer TB0 CCR5 capture input CCI5B
Timer TB0: TB0.5 compare output Out5
10
PM_TB0CCR6B
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.6 compare output Out6
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
11
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
12
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
13
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
14
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
15
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
16
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17
PM_MCLK
-
MCLK
18
Reserved
19
Reserved
20 - 30
Reserved
None
DVSS
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
31 (0FFh)(1)
PM_ANALOG
currents when applying analog signals.
(1)
The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are
ignored resulting in a read out value of 31.
Table 8. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCB0STE/PM_UCA0
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input) /
P2.0/P2MAP0
CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0SIMO/PM_UCB
USCI_B0 SPI slave in master out (direction controlled by USCI) / USCI_B0 I2C
P2.1/P2MAP1
0SDA
data (open drain and direction controlled by USCI)
PM_UCB0SOMI/PM_UCB
USCI_B0 SPI slave out master in (direction controlled by USCI) / USCI_B0 I2C
P2.2/P2MAP2
0SCL
clock (open drain and direction controlled by USCI)
PM_UCB0CLK/PM_UCA0
USCI_B0 clock input/output (direction controlled by USCI) / USCI_A0 SPI slave
P2.3/P2MAP3
STE
transmit enable (direction controlled by USCI - input)
Copyright 2010, Texas Instruments Incorporated
19
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