參數(shù)資料
型號: MSP430F6631IZQW
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PBGA113
封裝: PLASTIC, BGA-113
文件頁數(shù): 20/105頁
文件大?。?/td> 1077K
代理商: MSP430F6631IZQW
PRODUCTPREVIEW
MSP430F663x
www.ti.com
SLAS566A – JUNE 2010 – REVISED JULY 2010
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 9. System Module Interrupt Vector Registers
INTERRUPT VECTOR
INTERRUPT EVENT
WORD ADDRESS
OFFSET
PRIORITY
REGISTER
No interrupt pending
00h
Brownout (BOR)
02h
Highest
RST/NMI (BOR)
04h
DoBOR (BOR)
06h
LPM5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SYSRSTIV , System Reset
019Eh
SVMH_OVP (POR)
12h
DoPOR (POR)
14h
WDT timeout (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
FLL unlock (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
Lowest
No interrupt pending
00h
SVMLIFG
02h
Highest
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
SYSSNIV , System NMI
VMAIFG
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
Lowest
No interrupt pending
00h
NMIFG
02h
Highest
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
BUSIFG
08h
Reserved
0Ah to 1Eh
Lowest
No interrupt pending
00h
SYSBERRIV, Bus Error
USB wait state timeout
0198h
02h
Highest
Reserved
04h to 1Eh
Lowest
Copyright 2010, Texas Instruments Incorporated
21
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