參數(shù)資料
型號(hào)： MSX340-PB480
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： PLASTIC, BGA-480
文件頁數(shù)： 17/61頁
文件大?。?/td> 1437K
代理商： MSX340-PB480
MSX Family Data Sheet
24
[Rev. 1.10] 9/5/01
I-Cube, Inc.
2. Pin Description
Pin Name
Type
Description
P[531:000]
Bi-directional
Input/Output Signals.
OE[3:0]#
Input
Global Output Enables. Each output enable can control two of the four I/O banks.
Signal
MSX532 Connected I/O’s
MSX340 Connected I/O’s
OE_0#
P399-P531, P000-P132
P255-P339, P000-P084
OE_1#
P000-P132, P133-P265
P000-P084, P085-P169
OE_2#
P133-P265, P266-P398
P085-P169, P170-P254
OE_3#
P266-P398, P399-P531
P170-P254, P255-P339
IE[3:0]
Input
Global Input Enables. Each input enable can control two of the four I/O banks.
Signal
MSX532 Connected I/O’s
MSX340 Connected I/O’s
IE_0
P399-P531, P000-P132
P255-P339, P000-P084
IE_1
P000-P132, P133-P265
P000-P084, P085-P169
IE_2
P133-P265, P266-P398
P085-P169, P170-P254
IE_3
P266-P398, P399-P531
P170-P254, P255-P339
UPDATE
Input
Global Update
CLK[3:0]
Input
Global Clocks. Each clock can control two of the four I/O banks.
Signal
MSX532 Connected I/O’s
MSX340 Connected I/O’s
CLK_0
P399-P531, P000-P132
P255-P339, P000-P084
CLK_1
P000-P132, P133-P265
P000-P084, P085-P169
CLK_2
P133-P265, P266-P398
P085-P169, P170-P254
CLK_3
P266-P398, P399-P531
P170-P254, P255-P339
HW_RST#
Input
Hardware Reset.
RCE
Input
RapidConfigure Mode Select. Determines which programming mode that the device powers
up in.
0 = JTAG mode (RapidConfigure disabled)
1 = RapidConfigure mode (JTAG, IOB, Crosspoint programming disabled)
RC Pins
RC_CLK
Input
RapidConfigure Clock.
RC_EN#
Input
RapidConfigure Cycle Enable.
RCA[9:0]
Bi-directional
RapidConfigure Address A.
RCB[9:0]
Bi-directional
RapidConfigure Address B.
RCC[0]
Bi-directional
RapidConfigure Program Variable C.
RCC[3:1]
Input
RapidConfigure Program Variable C.
RCI[1:0]
Input
RapidConfigure Instruction Bits.
RC_RDY
Output
Read out IOB and connect/disconnect status.
JTAG Pins
TCK
Input
JTAG Test Clock.
TDI
Input
JTAG Test Data In.
TDO
Output
JTAG Test Data Out.
TMS
Input
JTAG Test Mode Select.
TRST#
Input
JTAG Test Reset.
Power and Ground Pins
VDD
Power
+3.3V power for the chip.
VSS
Ground
Ground for the chip. Tie these pins to system ground.
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