參數(shù)資料
型號(hào)： MSX340-PB480
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： PLASTIC, BGA-480
文件頁(yè)數(shù)： 2/61頁(yè)
文件大?。?/td> 1437K
代理商： MSX340-PB480
MSX Family Data Sheet
10
[Rev. 1.10] 9/5/01
I-Cube, Inc.
Array Side Force 0 – In this input mode, the Switch Matrix line is
forced low (logic 0), regardless of the signal on the corresponding I/O
Port. In this mode an optional input enable (IE) can be selected.
A0
Array Side Force 1 – In this input mode, the Switch Matrix line is
forced high (logic 1), regardless of the signal on the corresponding I/O
Port. In this mode an optional input enable (IE) can be selected.
A1
Bidirectional Transceiver with Register Input – This mode
combines Registered Input and buffered Output (OP). This mode
requires a clock source (CLK), and input enable (IE) and output enable
(OE#).
BT & RI
Bidirectional Transceiver with Register Output – This mode
combines Registered Output (RO) and buffered Input (IE). This mode
requires a clock source (CLK), and input enable (IE) and output enable
(OE#).
The output data inversion mode is NOT available to invert the output
signal.
BT & RO
Bidirectional Transceiver with Register I/O – This mode combines
Registered Input (RI) and Registered Output (RO). This mode requires
a clock source (CLK), and input enable (IE) and output enable (OE#).
The output data inversion mode is NOT available to invert the output
signal.
BT, RI
&RO
Table 1
Summary for Programmable I/O Attributes for MSX Devices (Continued)
Symbol
I/O Port Function
Mnemonic
Ax
Px
Ax
Px
DQ
IE
Ax
Px
CLK
OE
DQ
IE
Ax
Px
CLK
OE
D
1
Q
1
IE
Ax
Px
CLK_IN
OE
CLK_OP
Q
0
D
0
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