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參數(shù)資料
| 型號： | MSX532-TB792 |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | DSP-CROSSBAR SWITCH, PBGA792 |
| 封裝： | TBGA-792 |
| 文件頁數(shù)： | 54/61頁 |
| 文件大?。?/td> | 1437K |
| 代理商： | MSX532-TB792 |
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MSX Family Data Sheet
58
[Rev. 1.10] 9/5/01
I-Cube, Inc.
7. Glossary
ARRAY SIDE: The signal and connections between the Crosspoint Array and the IO Buffer.
BUS REPEATER: A circuit operation of the IO Buffer that enables the MSX device to pass data in both
directions on an IO device pin. The IO Buffer is placed in a disabled output state to the pin and to the Crosspoint
array. A forced low on either side of the IO Buffer will be transmitted to the other side of the IO Buffer and held
until the forced low is changed to a force high. At the change of the forcing input, the IO Buffer will force the
other side to a following high state and drive a high level out for a period of time. After the period of time, the
IO Buffer will return to the disabled state.
BYPASS: A JTAG instruction that connects the previous chip to the next chip through a one bit data register to
speed up programming of other chips in a JTAG chain of devices.
CLOCK: Four device corner inputs used to gate data into registers in the IO Buffer. The Corner inputs serve
two sides of the MSX. This provides two choices for each IO Buffer register in and register out. The neighbor
input can also be used as register clock and the clocks can be inverted.
CONTROL REGISTER: A programmable register used to control various functions in programming and other
circuit settings. All Bits programmed in the JTAG Mode. Rapid Configure Enable bit can be set with a high level
on the RCE pin during a reset of the circuits.
CROSSPOINT: A single cell containing two N Channel transistors and two RAM bits. The RAM bits are
connected in a master-slave configuration to provide an update for programming and changing program
information all at once. Each cell contains both an X and Y reset to remove all ports connected to an addressed
port in a single program cycle.
CROSSPOINT ARRAY: An array of Crosspoint used to connect any port to any other port or any combination
of other ports. The array has all redundant cell removed; there is a single Crosspoint cell for each port to port
connection. The reduced cell count is folded to provide a square array. The array has a diagonal line where the
cells are rotated.
DATA BIT LINES: A pair of signal lines used to write into and read out of Crosspoint Cells. The lines are pre-
charged before a read and one is pulled low for a write.
DEVICE ID: A 32-bit register in the MSX device with a wired identification. The ID consists of a given
number for the device and a revision history field. The identification is shifted out during JTAG reset and the
DEVICE ID instruction in JTAG mode. The ID for the MSX devices is 0x0000A89F.
EXTEST: A JTAG instruction that samples I/O pin states and loads new I/O buffer states for testing device pin
connections. The MSX devices use a special test mode in EXTEXT to observe the buffer data on the pin side and
the array side. A bit in the CONTROL REGISTER controls this mode.
IO BUFFER: The circuit that controls the driving of its associated pin and its port into and out of the Crosspoint
Array. The buffer contains all the circuits to make it independent of the other IO Buffers. Each Buffer contains
registers for input and output, driving circuits for input and output, sense for Crosspoint Array input, and RAM
bits to hold programmed data controlling the function of the buffer.
INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with
selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on
either side of the IO Buffer.
JTAG: The Joint Test Action group is a committee to standardize scan testing of devices. The JTAG interface is
referred to as IEEE 1149.1. This is a five bit serial programming and testing method.
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