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參數(shù)資料
| 型號(hào)： | MSX532-TB792 |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | DSP-CROSSBAR SWITCH, PBGA792 |
| 封裝： | TBGA-792 |
| 文件頁數(shù)： | 59/61頁 |
| 文件大?。?/td> | 1437K |
| 代理商： | MSX532-TB792 |
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MSX Family Data Sheet
I-Cube, Inc.
[Rev. 1.10] 9/5/01
7
1. Introduction
1.1
Switch Matrix
The MSX family are SRAM-based, bit-oriented switching devices. The main functional block of the device is a
Switch Matrix as shown in Figure 1. The Switch Matrix is an x-y routing structure (or grid). Each horizontal
signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots. An I/O Port pin
connects to this horizontal-vertical trace pair through programmable buffer. Signal paths through the Switch
Matrix are well balanced, resulting in predictable and uniform pin-to-pin delays.
The two SRAM cells (shown in Figure 2) are arranged so that a double buffered scheme can be employed. The
Active SRAM cells are responsible for establishing connections in the switch matrix by turning ON a pass
transistor, while the Loading SRAM cell can be used to store a second configuration that can be transferred to
the Active SRAM cell at any time. If the UPDATE signal is asserted high, the contents of the Loading SRAM
cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken.
The UPDATE signal can be used to control when the switch matrix is reconfigured. For instance, as long as the
UPDATE signal is de-asserted (held low), the Loading SRAM cells for the entire switch matrix could be
changed without affecting the current configuration of the switch. When the UPDATE signal is asserted high, the
entire switch matrix would be reconfigured simultaneously. If the UPDATE signal is asserted continuously, all
crosspoint programming commands (generated by JTAG or RapidConfigure programming cycles) will take
effect immediately, since the Loading SRAM cell’s contents will be transferred directly to the Active SRAM
cell.
Figure 2
MSX Switch Matrix Diagram
1
0
2
34
567
I/O Port Pins
Permanent Connection
Pass Transistor
Loading
SRAM
Cell
Active
SRAM
Cell
Data
UPDATE
Programmable I/O Buffers
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