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參數(shù)資料
| 型號(hào)： | MT28C128564W18EFW-F606P856KTBWT |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA77 |
| 封裝： | FBGA-77 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | MT28C128564W18EFW-F606P856KTBWT |
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128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
09005aef80df9a45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
10
2004 Micron Technology. Inc.
Boot Configurations
The possible configurations for Flash die are shown
in Table 2 below. This table shows the possible config-
urations of the two Flash devices for either top boot or
bottom boot: F_CE1# and F_CE2# indicate to which
Flash die the configuration is referred.
MultiChip Packaging Considerations
Multichip packaging presents unique chal-
lenges when controlling complex memory devices.
The
MT28C128532W18/W30E
and
MT28C128564W18/W30E
devices
combine
two
Micron Flash devices with a single CellularRAM
device.
Unique IDs, State Machines, and
Registers
Each Flash device has a separate command state
machine (CSM) and status register (SR) and read con-
figuration register (RCR). The read configuration regis-
ter (RCR) settings are separate and can be different for
the upper and lower device. Each Flash device has its
own OTP, CFI, and device code. Depending on the boot
configuration of each Flash device, the OTP, CFI, and
device code information may differ.
Both Flash devices will share the same ManID,
either Micron (0x2Ch) or Intel (0x89h), which is
defined by the part number.
The CellularRAM memory has a refresh configura-
tion register (RCR) that defines how the device per-
forms self refresh, and a bus configuration register
(BCR) to define the interface configuration.
Command Codes
All Flash command codes are independent
within each device. Care must be taken when
crossing the array boundary between the upper
and lower Flash and the CellularRAM memory to
ensure that only one device is enabled at one time.
In a two-cycle command sequence such as word
program (0x40/data), it is required that both com-
mands be issued to the same device.
It is not recommended that simultaneous READ,
simultaneous WRITE, or simultaneous ERASE opera-
tions occur on both Flash devices.
READ Operation
All READ operations are limited to the address
boundaries of each device. A new READ operation
must be started when crossing a device boundary.
Flash Reset
The reset control is shared by both Flash die.
Bringing F_RST# control LOW will reset both the
upper and lower device.
WAIT Ball Operation
It is important to note that the Flash and Cellular-
RAM devices share the WAIT ball functionality and
must be configured correctly for proper burst mode
operation. The Flash and CellularRAM devices use dif-
ferent registers to configure the WAIT polarity and
have opposite default values.
The WAIT ball polarity for the Flash device is config-
ured by programming bit 10 in the read configuration
register (RCR). The default is active LOW.
The WAIT ball polarity for the CellularRAM device is
configured by programming bit 10 in the bus configu-
ration register (BCR). The default is active HIGH.
Both the Flash and CellularRAM WAIT ball polarities
must be set to the same active level for proper opera-
tion.
Power Consumption
Multiple chip packaging requires that power
calculations consider the active operation of the
upper and lower Flash as well as that of the
CellularRAM device. Total power consumed will be
the sum of the currents associated with the state
of each device.
Table 2:
Possible Boot Configurations
for Flash Die
CONFIGURATION
F_CE2#
F_CE1#
ORDER
CODE
Top/Top
Top
TT
Top/Bottom
Top
Bottom
TB
Bottom/Top
Bottom
Top
BT
Bottom/Bottom
Bottom
BB
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