參數(shù)資料
型號(hào)： MT28C128564W18EFW-F606P856TBWT
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA77
封裝： FBGA-77
文件頁(yè)數(shù)： 15/15頁(yè)
文件大?。?/td> 203K
代理商： MT28C128564W18EFW-F606P856TBWT
128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
09005aef80df9a45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
9
2004 Micron Technology. Inc.
Table 1:
Ball Descriptions
77-BALL FBGA
NUMBERS
SYMBOL
TYPE
DESCRIPTIONS
F1, E1, D1, C1, A1,
B1, E2, D2, E6, C7,
D7, A8, B8, C8, E7,
D8, E8, C2, A2, A3,
D6, A7
A0–A21
Input
Addresses:
Flash: A0–A21 (128Mb).
CellularRAM: A0–A21 (64Mb).
CellularRAM: A0–A20 (32Mb).
J1
F_CE1#
Input
Flash Chip Enable #1.
F8
F_CE2#
Input
Flash Chip Enable #2.
H2
F_OE1#
Input
Flash Output Enable #1.
G8
F_OE2#
Input
Flash Output Enable #2.
E5
F_WE#
Input
Flash Write Enable.
D4
F_WP#
Input
Flash Write Protect.
E4
F_RST#
Input
Flash Reset.
B2
C_LB#
Input
CellularRAM Lower Byte Control.
E3
C_UB#
Input
CellularRAM Upper Byte Control.
C5
C_WE#
Input
CellularRAM Write Enable.
G1
C_OE#
Input
CellularRAM Output Enable.
C6
C_CE#
Input
CellularRAM Chip Enable.
J8
C_CRE
Input
CellularRAM Deep Sleep Mode and Configuration Mode.
D5
ADV#
Input
Address Valid (burst operation only).
B6
CLK
Input
Clock (burst operation only).
G2, G3, F3, G4, H5,
F5, H6, G7, F2, H3,
F4, H4, G5, F6, G6,
H7
DQ0–DQ15
I/O
Flash/CellularRAM Data Input/Output.
F7
WAIT#
Output
K7
F_VSS
Supply
Flash Core Ground.
C4
F_VPP
Supply
Flash VPP.
A5, A6, J6, K4
F_VCC
Supply
Flash Core Power Supply.
A4, B4, K1, K5, K8
C_VSS
Supply
CellularRAM Core Ground.
J5
C_VCC
Supply
CellularRAM Core Power Supply.
H8, J7, K3
VCCQ
Supply
Flash/CellularRAM I/O Supply.
K2, K6
VSSQ
Supply
Flash/CellularRAM I/O Ground.
B5, H1, J2, J3, J4
NC
–
No Connect. Not internally connected to the die.
B7
RFU
–
Reserved for Future Use (A22).
B3, C3, D3
–
Ball not Mounted. Reserved for Future Use (A23, A24, A25).
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