參數(shù)資料
型號(hào): MT46V32M4TG-8
廠商: Micron Technology, Inc.
英文描述: DOUBLE DATA RATE DDR SDRAM
中文描述: 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁(yè)數(shù): 67/68頁(yè)
文件大?。?/td> 2547K
代理商: MT46V32M4TG-8
67
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
WRITE
DM OPERATION
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
t
IS
t
IH
RA
t
RCD
t
RAS
t
DSH
7
tRP
tWR
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T4n
NOTE:
1. DI
n
= data-out from column
n
; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4.
Don
t Care
if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7
.tDSH is applicable during tDQSS
(MIN)
and is referenced from CK T4 or T5.
8
.tDSS is applicable during tDQSS
(MAX)
and is referenced from CK T5 or T6.
NOP6
NOP6
COMMAND
5
3
ACT
RA
RA
Col
n
WRITE2
NOP6
ONE BANK
ALL BANKS
Bank
x
PRE
Bank
x
NOP6
NOP6
NOP6
t
DQSL
t
DQSH
t
WPST
t
DSS
8
t
DSH
7
t
DSS
8
Bank
x
4
DQ
1
DQS
DM
DI
b
t
DS
t
DH
DON
T CARE
TRANSITIONING DATA
t
DQSS
(NOM)
t
WPRES
t
WPRE
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x8: A11
x16: A9, A11
TIMING PARAMETERS
-75Z
-75
-8
SYMBOL
t
DSH
t
IH
t
IS
t
RAS
t
RCD
t
RP
t
WPRE
t
WPRES
t
WPST
t
WR
MIN
0.2
1
1
45
20
20
0.25
0
0.4
15
MAX
MIN
0.2
1
1
45
20
20
0.25
0
0.4
15
MAX
MIN
0.2
1.1
1.1
50
20
20
0.25
0
0.4
15
MAX
UNITS
t
CK
ns
ns
ns
ns
ns
t
CK
ns
t
CK
ns
-75Z
-75
-8
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DQSH
t
DQSL
t
DQSS
t
DSS
MIN
0.45
0.45
7.5
7.5
0.5
0.5
0.35
0.35
0.75
0.2
MAX
0.55
0.55
13
13
MIN
0.45
0.45
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
MAX
0.55
0.55
13
13
MIN
0.45
0.45
8
10
0.6
0.6
0.35
0.35
0.75
0.2
MAX
0.55
0.55
13
13
UNITS
t
CK
t
CK
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
1.25
1.25
1.25
120,000
120,000
120,000
0.6
0.6
0.6
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