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參數(shù)資料
| 型號： | MT46V4M32 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 1/66頁 |
| 文件大?。?/td> | 1921K |
| 代理商： | MT46V4M32 |
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1
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
DOUBLE DATA RATE
(DDR) SDRAM
MT46V4M32 - 1 Meg x 32 x 4 banks
Web site: www.micron.com/dramds
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
FEATURES
V
DD
= +2.5V ±0.125V, V
DD
Q = +2.5V ±0.125V
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Reduced and matched output drive options
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data
Programmable burst lengths: 2, 4, 8, or full page
32ms, 4,096-cycle auto refresh
Auto precharge option
Auto Refresh and Self Refresh Modes
2.5V I/O (SSTL_2 compatible)
DQS per byte on the FBGA package
1.8V V
DD
Q option for FBGA package
t
RAS lockout
OPTIONS MARKING
Configuration
4 Meg x 32 (1 Meg x 32 x 4 banks)
IO Voltage
2.5V V
DD
Q
1.8V V
DD
Q
Plastic Packages
100-pin TQFP (0.65mm lead pitch)
12mm x 12mm FBGA
Timing - Cycle Time
300 MHz @ CL = 5
250 MHz @ CL = 4
200 MHz @ CL = 3
4M32
None
V1
LG
FK
-33
1
-4
1
-5
Note: 1. -4 and -33 speed grades are only available in the FBGA package
D
V
S
Q
D
D
V
D
V
D
Q
D
N
V
S
Q
D
N
N
N
N
V
D
Q
V
S
D
D
V
S
Q
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
313233343536
38 3940414243
37
45 4647484950
44
100999897969594939291 90 89888786 8584838281
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
V
REF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
A
A
A
A
V
D
A
A
N
N
N
N
N
N
N
A
V
S
A
A
A
A
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
4 Meg x 32
1 Meg x 32 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
256 (A0-A7)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
128Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V4M32LG
ARCHITECTURE
4 Meg x 32
Part Number Example:
MT46V4M32V1FK-33
KEY TIMING PARAMETERS
SPEED
GRADE
-33
-4
-5
CLOCK RATE
CL = 4
1
DATA-OUT
WINDOW
2
WINDOW
0.685ns
ACCESS
DQS-DQ
SKEW
CL = 5
1
300 MHz 250 MHz
-
-
CL = 3
1
-
±0.6ns +0.40ns
±0.7ns +0.45ns
±0.7ns +0.45ns
250 MHz 200 MHz 0.950ns
-
200 MHz 1.400ns
1. CL = CAS (Read) Latency
2. Minimum clock rate @ max CL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V4M32LG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
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