參數(shù)資料
型號(hào)： MT48LC4M16A2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 2/55頁(yè)
文件大?。?/td> 1458K
代理商： MT48LC4M16A2
2
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
dress bits registered coincident with the READ or WRITE
command are used to select the starting column loca-
tion for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the
full page, with a burst terminate option. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.
The 64Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2
n
rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge time
and the capability to randomly change column
addresses on each clock cycle during a burst access.
GENERAL DESCRIPTION
The Micron
64Mb SDRAM is a high-speed CMOS,
dynamic
random-access
67,108,864 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 16,777,216-bit banks is orga-
nized as 4,096 rows by 1,024 columns by 4 bits. Each of
the x8’s 16,777,216-bit banks is organized as 4,096 rows
by 512 columns by 8 bits. Each of the x16’s 16,777,216-
bit banks is organized as 4,096 rows by 256 columns by
16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The ad-
memory
containing
64Mb SDRAM PART NUMBERS
PART NUMBER
MT48LC16M4A2TG
MT48LC8M8A2TG
MT48LC4M16A2TG
ARCHITECTURE
16 Meg x 4
8 Meg x 8
4 Meg x 16
相關(guān)PDF資料
PDF描述
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