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| 型號： | MT48LC4M16A2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 25/55頁 |
| 文件大小： | 1458K |
| 代理商： | MT48LC4M16A2 |
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25
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the
SDRAM
supports
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
CONCURRENT
AUTO
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank
m
will interrupt a READ
on bank
n
, CAS latency later. The PRECHARGE to
bank
n
will begin when the READ to bank
m
is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank
m
will interrupt a READ
on bank
n
when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank
n
will
begin when the WRITE to bank
m
is registered
(Figure 25).
Figure 24
READ With Auto Precharge Interrupted by a READ
Figure 25
READ With Auto Precharge Interrupted by a WRITE
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
NOP
NOP
NOP
D
IN
d
+ 1
D
IN
d
D
IN
d
+ 2
D
IN
d
+ 3
NOP
T7
BANK
n
BANK
m
ADDRESS
Idle
NOP
DQM
NOTE:
1. DQM is HIGH at T2 to prevent D
OUT
-
a
+1 from contending with D
IN
-
d
at T4.
BANK
n
,
COL
a
BANK
m
,
COL
d
WRITE - AP
BANK
m
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP -
BANK
n
tWR -
BANK
m
CAS Latency = 3 (BANK
n
)
READ - AP
BANK
n
1
DON’T CARE
TRANSITIONING DATA
DON’T CARE
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK
n
NOP
NOP
NOP
NOP
D
OUT
a
+ 1
D
OUT
d
D
OUT
d
+ 1
NOP
T7
BANK
n
CAS Latency = 3 (BANK
m
)
BANK
m
ADDRESS
Idle
NOP
NOTE:
DQM is LOW.
BANK
n
,
COL
a
BANK
m
,
COL
d
READ - AP
BANK
m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK
n
tRP - BANK
m
CAS Latency = 3 (BANK
n
)
TRANSITIONING DATA
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