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| 型號： | MT48V8M16LFB4-8XT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件頁數(shù)： | 17/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48V8M16LFB4-8XT |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
24
2001 Micron Technology, Inc. All rights reserved.
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, pro-
vided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a single-
cycle delay should occur between the last read data
and the WRITE command.
Figure 16: READ to WRITE
The DQM input is used to avoid I/O contention, as
shown in Figure 16 and Figure 17. The DQM signal
must be asserted (HIGH) at least two clocks prior to
the WRITE command (DQM latency is two clocks for
output buffers) to suppress data-out from the READ.
Once the WRITE command is registered, the DQs will
go High-Z (or remain High-Z), regardless of the state of
the DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated
the READ command. If not, the second WRITE will be
an invalid WRITE. For example, if DQM was LOW dur-
ing T4 in Figure 17, then the WRITEs at T5 and T7
would be valid, while the WRITE at T6 would be
invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for
input buffers) to ensure that the written data is not
masked. Figure 16 shows the case where the clock fre-
quency allows for bus contention to be avoided with-
out adding a NOP cycle, and Figure 17 shows the case
where the additional NOP is needed.
Figure 17: READ to WRITE with Extra
Clock Cycle
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a PRE-
CHARGE command to the same bank. The PRE-
CHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Figure 18 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or
the last desired of a longer burst. Following the PRE-
CHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that
part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
DON’T CARE
READ
NOP
WRITE
NOP
CLK
T2
T1
T4
T3
T0
DQM
DQ
DOUT n
COMMAND
DIN b
ADDRESS
BANK,
COL n
BANK,
COL b
DS
tHZ
t
tCK
NOTES:
1) A CAS latency of three is used for illustration.
2) The READ command may be to any bank, and the WRITE
command may be to any bank.
3) If a burst of one is used, then DQM is not required.
TRANSITIONING DATA
DON’T CARE
READ
NOP
DQM
CLK
DQ
DOUT n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
DIN b
BANK,
COL b
T5
DS
tHZ
t
NOTE:
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
TRANSITIONING DATA
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| MT48V8M16LFF4-8 XT | 制造商:Micron Technology Inc 功能描述: |
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