- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296642 > MT4JSF6464HY-1G4XX 64M X 64 DDR DRAM MODULE, ZMA204 PDF資料下載
參數(shù)資料
| 型號： | MT4JSF6464HY-1G4XX |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, ZMA204 |
| 封裝： | LEAD FREE, SODIMM-204 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 618K |
| 代理商： | MT4JSF6464HY-1G4XX |
PDF: 09005aef82b2f090/Source: 09005aef82b2f012
Micron Technology, Inc., reserves the right to change products or specifications without notice.
JSF4C64_64x64HY.fm - Rev. B 3/08 EN
4
2007 Micron Technology, Inc. All rights reserved
512MB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Symbol
Type
Description
A[12:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set. A[12:0] address the 1Gb DDR3 devices.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
CK0, CK0#
Input
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
CKE0
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
DM[7:0]
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is
designed to match that of the DQ and DQS pins.
ODT0
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will
be ignored if disabled via the LOAD MODE command.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW CMOS input referenced to VSS.The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥ 0.8 × VDDQ and DC LOW ≤
0.2 × VDDQ. RESET# assertion and deassertion are asynchronous. System applications will
most likely be unterminated, heavily loaded, and have very slow slew rates. A slow slew
rate receiver design is recommended along with implementing on-chip noise filtering to
prevent false triggering (RESET# assertion minimum pulse width is 100ns).
S0#
Input
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
SA[1:0]
Input
Serial address inputs: These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize the
communication to and from the temperature sensor/SPD EEPROM.
DQ[63:0]
I/O
Data input/output: Bidirectional data bus.
DQS[7:0],
DQS#[7:0]
I/O
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
SDA
I/O
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I2C bus.
EVENT#
Output
(open drain)
Temperature event: The EVENT# pin is asserted by the temperature sensor when
critical temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the
module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address (VDD/2).
VREFDQ
Supply
Reference voltage: DQ, DM (VDD/2).
VSS
Supply
Ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT4LC16M4A7DJ-6S | 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32 |
| MT58L128L36P1T-5 | 128K X 36 CACHE SRAM, 2.8 ns, PQFP100 |
| MT58L512Y36FT-8.5 | 512K X 36 CACHE SRAM, 8.5 ns, PQFP100 |
| MT58V1MV18DT-10 | 1M X 18 CACHE SRAM, 5 ns, PQFP100 |
| MT5C2565EC-70/IT | 64K X 4 STANDARD SRAM, 70 ns, CQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4JTF12864AZ-1G1D1 | 功能描述:MOD DDR3 SDRAM 1GB 240UDIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT4JTF12864AZ-1G1DZES | 制造商:Micron Technology Inc 功能描述:1GB 128MX64 DDR3 SDRAM MODULE COMMERCIAL PBF DIMM GREEN 1.5V - Trays |
| MT4JTF12864AZ-1G4D1 | 功能描述:MOD DDR3 SDRAM 1GB 240UDIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT4JTF12864AZ-1G4DZES | 制造商:Micron Technology Inc 功能描述:1GB 128MX64 DDR3 SDRAM MODULE COMMERCIAL PBF DIMM GREEN 1.5V - Trays |
| MT4JTF12864AZ-1G6D1 | 功能描述:MOD DDR3 SDRAM 1GB 240UDIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復。