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參數(shù)資料
| 型號： | MT4LC16M4A7DJ-6S |
| 元件分類： | DRAM |
| 英文描述： | 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 338K |
| 代理商： | MT4LC16M4A7DJ-6S |
1
16 Meg x 4 FPM DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00
2000, Micron Technology, Inc.
16 MEG x 4
FPM DRAM
OBSOLETE
FEATURES
Single +3.3V ±0.3V power supply
Industry-standard x4 pinout, timing, functions,
and packages
13 row, 11 column addresses (A7)
12 row, 12 column addresses (T8)
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-compat-
ible
FAST-PAGE-MODE (FPM) access
4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
Optional self refresh (S) for low-power data
retention
OPTIONS
MARKING
Refresh Addressing
4,096 (4K) rows
T8
8,192 (8K) rows
A7
Plastic Packages
32-pin SOJ (400 mil)
DJ
32-pin TSOP (400 mil)
TG
Timing
50ns access
-5
60ns access
-6
Refresh Rates
Standard Refresh
None
Self Refresh (128ms period)
S*
NOTE: 1. The 16 Meg x 4 FPM DRAM base number
differentiates the offerings in one place—
MT4LC16M4A7. The fifth field distinguishes
various options: A7 designates an 8K refresh and
T8 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4A7DJ
DRAM
MT4LC16M4A7, MT4LC16M4T8
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tPC
tAA
tCAC
-5
90ns
50ns
30ns
25ns
13ns
-6
110ns
60ns
35ns
30ns
15ns
16 MEG x 4 FPM DRAM PART NUMBERS
REFRESH
PART NUMBER
ADDRESSING PACKAGE REFRESH
MT4LC16M4A7DJ-x
8K
SOJ
Standard
MT4LC16M4A7DJ-x S
8K
SOJ
Self
MT4LC16M4A7TG-x
8K
TSOP
Standard
MT4LC16M4A7TG-x S
8K
TSOP
Self
MT4LC16M4T8DJ-x
4K
SOJ
Standard
MT4LC16M4T8DJ-x S
4K
SOJ
Self
MT4LC16M4T8TG-x
4K
TSOP
Standard
MT4LC16M4T8TG-x S
4K
TSOP
Self
x = speed
32-Pin TSOP
32-Pin SOJ
PIN ASSIGNMENT (Top View)
VCC
DQ0
DQ1
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
DQ3
DQ2
NC
CAS#
OE#
A12/NC**
A11
A10
A9
A8
A7
A6
VSS
**A12 on A7 version and NC on T8 version
VCC
DQ0
DQ1
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
DQ3
DQ2
NC
CAS#
OE#
A12/NC**
A11
A10
A9
A8
A7
A6
VSS
GENERAL DESCRIPTION
The 16 Meg x 4 DRAMs are high-speed CMOS,
dynamic random-access memory devices contain-ing
67,108,864 bits organized in a x4 configuration. The
MT4LC16M4A7 and MT4LC16M4T8 are functionally
organized as 16,777,216 locations containing four bits
each. The 16,777,216 memory locations are arranged in
8,192 rows by 2,048 columns for the MT4LC16M4A7 or
4,096 rows by 4,096 columns for the MT4LC16M4T8.
During READ or WRITE cycles, each location is uniquely
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4LC16M4A7TG-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC16M4A7TG-5S | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC16M4A7TG-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC16M4A7TG-6S | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC16M4G3 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
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