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參數(shù)資料
| 型號(hào)： | MT80C51C-12R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 29/109頁 |
| 文件大小： | 10824K |
| 代理商： | MT80C51C-12R |
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274
7593L–AVR–09/12
AT90USB64/128
7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
2 - LSM - USB Device Low Speed Mode selection
When configured USB is configured in device mode, this bit allows to select the USB the USB
Low Speed or Full Speed Mod.
Clear to select full speed mode (D+ internal pull-up will be activate with the ATTACH bit will be
set) .
Set to select low speed mode (D- internal pull-up will be activate with the ATTACH bit will be
set). This bit has no effect when the USB interface is configured in HOST mode.
1- RMWKUP - Remote Wake-up bit
Set to send an “upstream-resume” to the host for a remote wake-up (the SUSPI bit must be set).
Cleared by hardware when signalling finished. Clearing by software has no effect.
See Section 23.10, page 266 for more details.
0 - DETACH - Detach bit
Set to physically detach de device (disconnect internal pull-up on D+ or D-).
Clear to reconnect the device. See Section 23.9, page 265 for more details.
7 - Reserved
The value read from this bits is always 0. Do not set this bit.
6 - UPRSMI - Upstream Resume Interrupt flag
Set by hardware when the USB controller is sending a resume signal called “Upstream
Resume”. This triggers an USB interrupt if UPRSME is set.
Shall be cleared by software (USB clocks must be enabled before). Setting by software has no
effect.
5 - EORSMI - End Of Resume Interrupt flag
Set by hardware when the USB controller detects a good “End Of Resume” signal initiated by
the host. This triggers an USB interrupt if EORSME is set.
Shall be cleared by software. Setting by software has no effect.
4 - WAKEUPI - Wake-up CPU Interrupt flag
Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the
lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is set. This interrupt
should be enable only to wake up the CPU core from power down mode.
Shall be cleared by software (USB clock inputs must be enabled before). Setting by software
has no effect.
See Section 23.8, page 265 for more details.
Bit
7
65432
1
0
-
UPRSMI
EORSMI
WAKEUPI
EORSTI
SOFI
-
SUSPI
UDINT
Read/write
Initial value
0
00000
0
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