參數(shù)資料
型號： MT8931B
廠商： Mitel Networks Corporation
英文描述： ()
中文描述： （）
文件頁數(shù)： 25/29頁
文件大?。?/td> 277K
代理商： MT8931B
Application Note
MSAN-141
A-225
in transparent data transfer state. However, the
FIFO related status and interrupt bits are pertinent
and carry the same meaning as they do while
performing the protocol functions.
9.0
APPLICATION HINTS
9.1
Power-up Conditions
In controllerless mode, the transfer of data between
the S-Bus and the ST-BUS is established on power
up or after a reset. However, the ST-BUS ports and
the HDLC transmitter and receiver are disabled on
power up or after a reset if the microprocessor mode
is selected. This prevents the transfer of data
between the ST-BUS, the HDLC transceiver, and the
S-Bus. To enable the transfer of data on the B1 and
B2 channels of the two serial ports, the user has to
set the corresponding bits in the ST-BUS Control
Register. The D-channel data, however, is routed
between the two serial ports and the HDLC
transceiver in various configurations as indicated in
section 9.3.
9.2
Controlling the SNIC
The C-channel on the ST-BUS DSTi stream can be
used to control the SNIC. When controllerless mode
is selected on the MT8930B, pin 11 (P/SC) is used to
indicate whether the microport pins or the DSTi C
channel is the control source of the device. If the C
channel is chosen, then the microport pins are
ignored. In microprocessor controlled mode,
however, bit 0 of the Master Control Register selects
either the parallel port or the C channel to be the
control source of the SNIC.
When the C channel is used to control the device, its
data is loaded into the C-channel Control Register.
When it is not used, the data on this channel is
discarded. The contents of the NT or TE Mode
Status Register (depending on the mode selected) is
always sent out on the C channel of ST-BUS DSTo
pin.
The microprocessor can overwrite any data
transferred between the S-Bus and the ST-BUS by
accessing the corresponding synchronous register.
9.3
D-Channel Switching
The D channel is routed between the HDLC
transceiver, the S-Bus, and the ST-BUS in different
ways.
Figure
29
configurations and the required condition to set each
of them. An “x” mark in the diagram is a “don’t care”
state meaning that the state of the corresponding bit
has no effect on the setting of the communication
path. Note that in all the configurations, the transfer
shows
these
possible
of data to and from the ST-BUS on the D channel is
enabled by setting respectively bits B4 and B0 of the
ST-BUS Control Register to 1.
9.4
HDLC Operation
This section outlines a recommended procedure for
transmitting, receiving, and monitoring the status of
HDLC packets. The HDLC protocol on the D-
channel of the S-Bus is enabled by initializing the
SNIC as follows:
1)
The TxEn, RxEn, TxPrtSel, and RxPrtSel bits in
the HDLC Control Register 1 should be set to
ONE.
2)
The HDLC Interrupt Mask Register bits should
be enabled so the device can issue interrupts
indicating the status of the HDLC FIFOs and
packets.
3)
The IFTF bit in the HDLC Control Register 1
should be set to 0 for a TE SNIC in passive bus
configuration. This will allow the device to
transmit continuous ONEs between packets thus
giving other TEs a chance to access the D-
channel.
After initialization, the packets should be transmitted
in the following sequence:
1)
D-channel bytes are written to the Tx FIFO.
Everytime a packet is to be closed, the EOP bit
in the HDLC Control Register 2 should be set to
ONE. This will tag the next byte written to the Tx
FIFO with the end-of-packet sequence (CRC bits
and the flag). A maximum of 19 bytes should be
written to avoid an overflow condition.
When the TxFIFO is loaded with more than one
packet at a time, then the closing flag of the first
transmitted packet will be used as the opening
flag of the next packet. This will violate CCITT
I.430 and ANSI T1.605 Recommendations
which specifies that a TE must lower its priority
level within the selected priority class after the
successful transmission of a packet. The user
can meet this requirement by loading the Tx
FIFO with no more than one packet and then
waiting for the DCack bit to go to zero, or for an
HDLC interrupt caused by the TEOP bit in the
HDLC
Interrupt
Status
attempting to load a new packet.
Register,
before
2)
When the device has only four remaining bytes
in the Tx FIFO, an interrupt is issued through the
TxFL bit in the HDLC Interrupt Status Register.
This is a warning indicating that more data
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