參數(shù)資料
型號(hào)： MT8952BPR
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28
封裝： PLASTIC, MS-018AB, LCC-28
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 602K
代理商： MT8952BPR
MT8952B
Data Sheet
17
Zarlink Semiconductor Inc.
Frame Abort
When a frame abort is received the appropriate bits in the Interrupt Flag and Status Registers are set. The last byte
of the packet that was aborted is written to the FIFO with a status of ‘packet byte’ tagged to it. The CPU determines
which packet in the FIFO was aborted, if there is more than one packet in the FIFO, by the absence of ‘last byte’
status on any of the bytes.
Idle Channel
While receiving the idle channel, the idle bit in the general status register remains set.
Go Ahead
The occurrence of this sequence can be used to generate an interrupt as described earlier. The receive circuitry will
not recognize a frame abort followed by a flag as go ahead.
C-Channel Reception
The information contained in channel-1 of the incoming ST-BUS (CDSTi) is shifted into the C-Channel Status
Register during the Internal Timing Mode.
Transparent Data Transfer
By setting the IFTF bits in the Control Register to select the transparent data transfer, the receive section can be
made to disable the protocol functions like Flag/Abort/GA/Idle detection, zero deletion, CRC calculation and
address comparison. The received data is shifted in from CDSTi and written to receive FIFO in bytewide format. If
the Protocol Controller is in the Internal Timing Mode and the Timing Control bits are set to 2, 6 or 7 bits/frame, the
respective MSBs of each byte are only to be read from the data bus. The transparent data transfer facility is not
available when the Timing Control bits are set to one bit/frame. The receive section can be disabled in software
immediately using the RxEN bit in the Control Register.
The operation of the receiver is similar in the External Timing Mode.
Receive Overflow
Receive overflow occurs when the receive section attempts to load a byte to an already full receive FIFO. This
status can be used to generate the interrupt as described earlier.
Typical Connection
A typical connection to the HDLC Protocol Controller is shown in Figure 14. The parallel port interfaces with
6800/6809 type processors. The bits A0-A3 are the addresses of various registers in the Protocol Controller. The
microprocessor can read and write to these registers treating them as memory locations.
The serial port transmits/receives the packetized data. It can be connected to a digital transmission medium or to a
digital network interface circuit. The TEOP and REOP are the ‘end of packet’ signals on transmit and receive
direction respectively. F0i and CKi are the timing signals with CKi accepting either the bit rate clock or 2 x bit rate
clock in the internal timing mode. TxCEN and RxCEN are the enable inputs in the External Timing Mode.
WD is the output of the watchdog timer. It goes LOW when the timer times out or if the RST input is held LOW. This
output can be used to reset the associated microprocessor. The RST is an active LOW
input which resets the
entire circuitry.
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