參數(shù)資料
型號(hào)： MT9040
廠商： Mitel Networks Corporation
英文描述： T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
中文描述： 的T1/E1同步（T1/E1的系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成））
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 82K
代理商： MT9040
Advance Information
MT9040
5
Four tapped delay lines are used to generate
16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz
signals.
The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and five frame pulse
outputs.
The
C8o,
C4o
generated by simply dividing the C16o clock by two,
four and eight respectively. These outputs have a
nominal 50% duty cycle.
and
C2o
clocks
are
The T1 Divider Circuit uses the 12.384MHz signal
to generate the C1.5o clock by dividing the internal
C12 clock by eight. This output has a nominal 50%
duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal
to generate the clock output C6o. This output has a
nominal 50% duty cycle.
Figure 4 - Output Interface Circuit Block
Diagram
The frame pulse outputs (F0o, F8o, F16o, TSP, and
RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a
common DPLL signal. Consequently, all frame pulse
and clock outputs are locked to one another for all
operating states, and are also locked to the input
reference in Normal Mode. See Figures 9,10 and 11.
All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for
a complete loss of incoming signal, or a large
frequency shift in the incoming signal. If the input
signal is outside the Impairment Monitor Capture
Range the PLL automatically changes from Normal
Mode
to
Free
Run
Mode.
Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal
returns to normal, the DPLL is returned to Normal
Mode.
See
AC
Electrical
Master Clock
The MT9040 can use either a clock or crystal as the
master timing source. For recommended master
timing circuits, see the Applications - Master Clock
section.
Control and Mode of Operation
The MT9040 has two possible modes of operation,
Normal and Freerun. As shown in Table 2, the Mode/
Control Select pin MS selects the mode.
Normal Mode
Normal Mode is typically used when a slave clock
source, synchronized to the network is required.
In Normal Mode, the MT9040 provides timing (C1.5o,
C2o,
C4o,
C8o,
C16o
synchronization (F0o, F8o, F16o, TSP and RSP)
signals, which are synchronized to the reference
input. The input reference signal may have a nominal
frequency
of
8kHz,
1.544MHz,
19.44MHz.
and
C19o)
and
frame
2.048MHz
or
From a reset condition, the MT9040 will take up to 30
seconds (see AC Electrical Characteristics) of input
reference
signal
to
output
synchronized (phase locked) to the reference input.
signals
which
are
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16MHz
12MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12MHz
19MHz
C6o
C19o
MS
Mode
0
NORMAL
1
FREERUN
Table 2 - Operating Modes and States
相關(guān)PDF資料
PDF描述
MT9041A ()
MT9041B T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
MT9042B ()
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MT9040AN 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Synchronizer
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