參數(shù)資料
型號(hào)： MT9044
廠商： Mitel Networks Corporation
英文描述： T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
中文描述： T1/E1/OC3系統(tǒng)同步器（T1/E1/OC3系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成））
文件頁(yè)數(shù)： 30/34頁(yè)
文件大?。?/td> 150K
代理商： MT9044
MT9044
30
Notes:
Voltages are with respect to ground (V
) unless otherwise stated.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1. PRI reference input selected.
2. SEC reference input selected.
3. Normal Mode selected.
4. Holdover Mode selected.
5. Freerun Mode selected.
6. 8kHz Frequency Mode selected.
7. 1.544MHz Frequency Mode selected.
8. 2.048MHz Frequency Mode selected.
9. Master clock input OSCi at 20MHz
0ppm.
10. Master clock input OSCi at 20MHz
±
32ppm.
11. Master clock input OSCi at 20MHz
±
100ppm.
12. Selected reference input at
0ppm.
13. Selected reference input at
±
32ppm.
14. Selected reference input at
±
100ppm.
15. For Freerun Mode of
0ppm.
16. For Freerun Mode of
±
32ppm.
17. For Freerun Mode of
±
100ppm.
18. For capture range of
±
230ppm.
19. For capture range of
±
198ppm.
20. For capture range of
±
130ppm.
21. 25pF capacitive load.
22. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz.
23. Jitter on reference input is less than 7nspp.
24. Applied jitter is sinusoidal.
25. Minimum applied input jitter magnitude to regain synchronization.
26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
27. Within 10ms of the state, reference or input change.
28. 1UIpp = 125us for 8kHz signals.
29. 1UIpp = 648ns for 1.544MHz signals.
30. 1UIpp = 488ns for 2.048MHz signals.
31. 1UIpp = 323ns for 3.088MHz signals.
32. 1UIpp = 244ns for 4.096MHz signals.
33. 1UIpp = 122ns for 8.192MHz signals.
34. 1UIpp = 61ns for 16.384MHz signals.
35. No filter.
36. 40Hz to 100kHz bandpass filter.
37. With respect to reference input signal frequency.
38. After a RST or TRST.
39. Master clock duty cycle 40% to 60%.
40. Prior to Holdover Mode, device was in Normal Mode and phase locked.
41. 1Ulpp = 51ns for 19.44MHz signals.
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