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參數(shù)資料
| 型號(hào)： | MT90733 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 52K |
| 代理商： | MT90733 |
Advance Information
CMOS
MT90733
5-25
Note: I = Input; O = Output; P = Power
Note: I = Input; O = Output; P = Power
Note: I = Input; O = Output; P = Power
DS3 Transmit Line Side Interfac
e
Pin #
Name
I/O/P
Description
1
D3TC
O
DS3 Transmit Clock.
A 44.736 MHz clock that is derived from the transmit
clock (XCK) signal and is used for clocking out the line side DS3 data signal.
3
D3TD
O
DS3 Transmit Data.
DS3 line side serial transmit data.
Receive Terminal Side Interfac
e
Pin #
Name
I/O/P
Description
31
RFS
/
RFN
O
Receive Framing Pulse for Serial/Nibble Interface.
The framing pulse is
synchronous with the first bit 1 in the DS3 frame or nibble 1175.
32
RCG
O
Receive Clock Gap Signal.
The active low gap signal is synchronous with
each overhead bit in the serial DS3 frame (first bit in the 85-bit group).
34
RCS/RCN
O
Receive Clock for Serial/Nibble Interface.
Clock used for clocking out the
terminal side receive serial and nibble data.
39
40
41
42
RNIB3
RNIB2
RNIB1
RDS/RNIB0
O
Receive Nibble/Serial Interface.
Nibble data is clocked out on positive transi-
tions of the nibble clock (RCN). Serial data is clocked out on negative transi-
tions of the receive clock (RCS).
Transmit Terminal Side Interfac
e
Pin #
Name
I/O/P
Description
2
XFNO
O
Transmit Framing Pulse for Nibble Interface.
An active low, one nibble clock
cycle wide (XCN) pulse that occurs during the second nibble time.
50
XFSI
I
Transmit Framing Pulse for Serial Interface:
A framing pulse input that must
be synchronous with bit 1 in the transmit serial data DS3 frame.
56
58
59
60
XDS/XNIB3
XNIB2
XNIB1
XNIB0
I
Transmit Nibble/Serial Interface.
Nibble data is clocked in on positive transi-
tions of the nibble clock (XCN). Serial data is clocked into the DS3F on posi-
tive transitions of the transmit clock (XCK).
62
XCK
I
Transmit Clock.
A 44.736 Mbit/s clock input with a stability of
±
20 ppm and a
duty cycle of 50
±
10%. XCK provides the time base for the transmitter in the
DS3F.
66
XCN
O
Transmit Clock for Nibble Interface.
Output clock signal derived from the
transmit clock (XCK).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9074 | T1/E1/J1 Single Chip Transceiver |
| MT9074AL | T1/E1/J1 Single Chip Transceiver |
| MT9074AP | T1/E1/J1 Single Chip Transceiver |
| MT9074 | T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90733AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS DS3 Framer (DS3F) |
| MT9074 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074AL | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays |
| MT9074AL1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays |
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