參數(shù)資料
型號(hào): MT9074AP
廠商: Mitel Networks Corporation
英文描述: T1/E1/J1 Single Chip Transceiver
中文描述: T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù): 1/122頁
文件大?。?/td> 372K
代理商: MT9074AP
1
MT9074
T1/E1/J1 Single Chip Transceiver
Features
Combined E1 (PCM 30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode
In T1 mode the LIU can recover signals attenuated
by up to 36 dB (6000 ft. of 24 AWG cable)
In E1 mode the LIU can recover signals attenuated
by up to 36 dB (2000 m. of 0.65mm cable)
Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode
Two-frame elastic buffer in Rx & Tx (T1) directions
Programmable transmit delay through transmit slip
buffer
Low jitter DPLL for clock generation
Enhanced alarms, performance monitoring and
error insertion functions
Intel or Motorola non-multiplexed parallel
microprocessor interface
ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling
Japan Telecom J1 Framing and Yellow Alarm
Hardware data link access
JTAG Boundary Scan
Applications
E1/T1 add/drop multiplexers and channel banks
CO and PBX equipment interfaces
Primary Rate ISDN nodes
Digital Cross-connect Systems (DCS)
Description
The MT9074 is a single chip device, operable in
either T1 or E1 mode, integrating either an advanced
T1 (T1 mode) or PCM 30 (E1 mode) framer with a
Line Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane
providing selectable data link access with optional
HDLC controllers for either the FDL bits and channel
24 (T1 mode) or S
a
bits and channel 16 (E1 mode).
The LIU interfaces the framer to T1 (T1 mode) or
PCM 30 (E1 mode) transformer-isolated four-wire
line with minimal external components required.
In T1 mode the MT9074 supports D4, ESF and SLC-
96 formats, meeting the latest recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T1.403 and T1.408. In E1 mode the
MT9074
supports
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also supports ETSI ETS 300
011, ETS 300 166 and ETS 300 233.
the
latest
ITU-T
Figure 1 - Functional Block Diagram
ST-BUS
Interface
CAS
Buffer
ST Loop
PL Loop
National
Bit Buffer
DG Loop
Alarm Detection, 2 Frame Slip Buffer
ST-BUS
Interface
M
I
TxAO TxB TxA
Line
Driver
TTIP
TRING
P
G
C
R
R
&
OSC2
RTIP
RRING
OSC1
CSTi
DSTi
CSTo
DSTo
E1.5o
F0b C4b
RxMF
LOS
TxMF
Transmit Framing, Error,
Test Signal Generation and Slip Buffer
Data Link,
HDLC0
HDLC1
Receive Framing, Performance Monitoring,
RxDLCLK RxDL
TxDL TxDLCLK
R/W/WR
CS
DS/RD
IRQ
D7~D0
AC4
AC0
RxFP
Jitter Attenuator
& Clock Control
L
L
Tdi
Tdo
Tms
Tclk
Trst
S/FR
DS5024
ISSUE 5
September 1999
Advance Information
Ordering Information
MT9074AP
MT9074AL
68 Pin PLCC
100 Pin MQFP
-40
°
C to 85
°
C
相關(guān)PDF資料
PDF描述
MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
MT9075A E1 Single Chip Transceiver
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