參數(shù)資料
型號(hào)： MT9075
廠(chǎng)商： Mitel Networks Corporation
英文描述： E1 Single Chip Transceiver
中文描述： 素E1單芯片收發(fā)器
文件頁(yè)數(shù)： 60/78頁(yè)
文件大?。?/td> 1008K
代理商： MT9075
MT9075A
Preliminary Information
4-188
Table 87 - HDLC Interrupt Status Register
(Page 0BH & 0CH, Address 17H) (continued)
Table 87 - HDLC Interrupt Status Register
(Page 0BH & 0CH, Address 17H)
Bit
Name
Functional Description
7-0
Ga,
EOPD,
TEOP,
EOPR,
TxFl,
FA:
Txunder,
RxFf &
RxOvfl
This register is used with the
Interrupt Register to mask out the
interrupts that are not required by
the microprocessor. Interrupts that
are masked out will not produce an
IRQ; however, they will set the
appropriate bit in the Interrupt
Register. An interrupt is disabled
when the microprocessor writes a 0
to a bit in this register. This register
is cleared on power reset.
Table 86 - HDLC Interrupt Mask Register
(Pages 0BH & 0CH, Address 16H)
Bit
Name
Functional Description
7
GA
Go-Ahead.
Indicates a go-ahead
pattern was detected by the HDLC
receiver. This bit is reset after a
read.
6
EOPD
End Of Packet Detect.
This bit is
set to one when an end of packet
(EOP) byte was written into the RX
FIFO by the HDLC receiver. This
can be in the form of a flag, an abort
sequence or as an invalid packet.
This bit is reset after a read.
5
TEOP
Transmit End Of Packet.
This bit is
set to one when the transmitter has
finished sending the closing flag of a
packet or after a packet has been
aborted. This bit is reset after read.
4
EOPR
End Of Packet Read.
This bit is set
to one when the byte about to be
read from the RX FIFO is the last
byte of the packet. It is also set to
one if the Rx FIFO is read and there
is no data in it. This bit is reset after
a read.
3
TxFL
TX FIFO Low.
This bit is set to one
when the TX FIFO is emptied below
the selected low threshold level.
This bit is reset after a read.
Bit
Name
Functional Description
2
FA:
Txunder
Frame Abort/TX FIFO Underrun.
When Intsel bit of Control Register 2
is low, this bit is set to one when a
frame abort is received during pack-
et reception. It must be received af-
ter a minimum number of bits have
been received (26) otherwise it is ig-
nored.
When Intsel bit of Control Register
2 is one, this bit is set to one for a
TX FIFO underrun indication. If one
it indicates that a read by the
transmitter was attempted on an
empty Tx FIFO.
This bit is reset after a read.
1
RxFf
RX FIFO Full.
This bit is set to one
when the RX FIFO is filled above
the selected full threshold level.
This bit is reset after a read.
0
RxOvfl
RX FIFO Overflow.
A one indicates
that the 128 byte RX FIFO
overflowed (i.e. an attempt to write
to a 128 byte full RX FIFO). The
HDLC will always disable the
receiver once the receive overflow
has been detected. The receiver
will be re-enabled upon detection of
the next flag, but will overflow again
unless the RX FIFO is read. This bit
is reset after a read.
Bit
Name
Functional Description
7 - 0
Crc15-8
The MSB byte of the CRC received
from the transmitter. These bits are
as the transmitter sent them; that is,
most
significant
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
bit
first
and
Table 88 - Receive CRC MSB Register
(Pages 0BH & 0CH, Address 18H)
相關(guān)PDF資料
PDF描述
MT9075A E1 Single Chip Transceiver
MT9075AL E1 Single Chip Transceiver
MT9075AP E1 Single Chip Transceiver
MT9075BL E1 Single Chip Transceiver
MT9075BP E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9075A 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver
MT9075AL 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver
MT9075AP 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver
MT9075B 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:E1 Single Chip Transceiver
MT9075B-1 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver
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