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參數(shù)資料
| 型號： | MT9075B-1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | E1 Single Chip Transceiver |
| 中文描述： | 素E1單芯片收發(fā)器 |
| 文件頁數(shù)： | 15/78頁 |
| 文件大?。?/td> | 1008K |
| 代理商： | MT9075B-1 |
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Preliminary Information
MT9075A
4-143
Table 6 - Reset Status
Transmit AIS Operation
The pin TAIS (Transmit AIS, pin 60 in PLCC, pin 48 in
MQFP) allows an all ones signal to be transmitted
from the point of power-up without the need to write
any control registers. During this time the IRQ pin is
tristated. After the interface has been initialized
normal operation can take place by making TAIS
high.
National Bit Buffers
Table 7 shows the contents of the transmit and
receive Frame Alignment Signals (FAS) and Non-
frame Alignment Signals (NFAS) of time slot zero of
a PCM 30 signal. Even numbered frames (CRC
Frame # 0, 2, 4,...) are FASs and odd numbered
frames (CRC Frame # 1, 3, 5,...) are NFASs. The bits
of each channel are numbered 1 to 8, with bit 1 being
the most significant and bit 8 the least significant.
Table 7 - FAS and NFAS Structure
Table 8 illustrates the organization of the MT9075A
transmit and receive national bit buffers. Each row is
an addressable byte of the MT9075A national bit
buffer, and each column contains the national bits of
an odd numbered frame of each CRC-4 Multiframe.
The transmit and receive national bit buffers are
located at page 0DH and 0EH respectively.
Table 8 - MT9075A National Bit Buffers
Note that the Data Link (DL) pin functions, if
selected, override the transmit national bit buffer
function.
Function
Mode
Loopbacks
Transmit FAS
Transmit non-FAS
Transmit MFAS (CAS)
Data Link
CRC Interworking
Signalling
ABCD Bit Debounce
Interrupts
Status
Termination
Deactivated
C
n
0011011
1/S
n
1111111
00001111
Deactivated
Activated
CAS Registers
Deactivated
Interrupt Mask Word
Zero unmasked, all
others masked;
interrupts not suspended
Signalling Multiframe
Deactivated
Deactivated
Cleared
All locations set to 54H
All locations cleared
RxMF Output
Error Insertion
HDLCs
Counters
Tx Message Buffer
Per Time Slot Control
Buffer
CRC
CRC
Frame/
Type
PCM 30 Channel Zero
1
2
3
4
5
6
7
8
S
0/FAS
C
1
0
0
1
1
0
1
1
1/NFAS
0
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
2/FAS
C
2
0
0
1
1
0
1
1
3/NFAS
0
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
4/FAS
C
3
0
0
1
1
0
1
1
5/NFAS
1
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
6/FAS
C
4
0
0
1
1
0
1
1
7/NFAS
0
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
8/FAS
C
1
0
0
1
1
0
1
1
9/NFAS
1
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
10/FAS
C
2
0
0
1
1
0
1
1
11/NFAS
1
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
12/FAS
C
3
0
0
1
1
0
1
1
13/NFAS
E
1
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
14/FAS
C
4
0
0
1
1
0
1
1
15/NFAS
E
2
1
A
S
a4
S
a5
S
a6
S
a7
S
a8
Addre
ssable
Bytes
Frames 1, 3, 5, 7, 9, 11, 13 & 15 of a CRC-4
Multiframe
F1
F3
F5
F7
F9
F11
F13
F15
NBB0
S
a4
S
a4
S
a4
S
a4
S
a4
S
a4
S
a4
S
a4
NBB1
S
a5
S
a5
S
a5
S
a5
S
a5
S
a5
S
a5
S
a5
NBB2
S
a6
S
a6
S
a6
S
a6
S
a6
S
a6
S
a6
S
a6
NBB3
S
a7
S
a7
S
a7
S
a7
S
a7
S
a7
S
a7
S
a7
NBB4
S
a8
S
a8
S
a8
S
a8
S
a8
S
a8
S
a8
S
a8
indicates position of CRC-4 multiframe alignment signa
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