參數(shù)資料
型號(hào): MT9085B
廠商: Mitel Networks Corporation
英文描述: PAC - Parallel Access Circuit(并行存取電路)
中文描述: 委員會(huì)-并行訪問電路(并行存取電路)
文件頁數(shù): 10/21頁
文件大?。?/td> 111K
代理商: MT9085B
MT9085B
2-134
In the example configuration shown in Figure 9 the
OE pin of PAC #2 is connected to D10 on the
Connection Memory. Setting bit 10 high in the
Connection Memory location corresponding to a
serial channel timeslot will result in the output driver
for the specific stream being disabled during that
serial channel timeslot. D11 is connected to the ME
input of SMX1 and D12 is connected to a mode
select pin (Mz). Consequently, the levels on these
outputs can be set high or low by writing to the
appropriate memory location corresponding to the
selected output channel. The mapping of the control
functions on to Connection Memory data bits is
illustrated in Figure 10.
The data on the PAC serial streams is byte
interleaved
as
described
Description section in this data sheet. The SMX
channel number corresponding to the channel on the
serial streams can be determined directly by
specifying the serial channel and stream number in
binary as shown in Figure 11. For example, serial
channel 4, stream 2 corresponds to SMX channel
in
the
Functional
number Hex 0082. In order to program the matrix for
switching, the input channel address is written to the
Connection Memory address corresponding to the
serial output channel. The bits controlling features
such as OE, ME, and Mz should be set or reset
accordingly at the same time. For example. if
channel 4 on stream 2 is to be switched to channel
10 on stream 1, the following binary word is written
to Connection Memory address corresponding to the
output channel (Hex 0141):
X X X 0
1 0 0 0
0 0 0 0
0 0 1 0
Stream Address
Channel Address
Output Enable
Message Enable
DM-1/DM-2
Unused
Figure 9 - 1024 Channel Switch Matrix Using the PAC and SMX
Timing
Source
C4i C16i
S0
S31
2/4S
OE CKD MCA MCB
P0-P7
DFPo
CFPo
PAC#1
S/P
F0i
S0
S31
C16
C4
F0
8
C16
+5
+5
D0-D7i
CK
FP
Mz
R/W
ODE
A0-A9 ME
D0-D7o
Mx
My
CS
DS
8
SMX #1
DM - 1/2
F0 C4 C16
F0i C4i C16i
P0-P7
OE CKD MCA
MCB
2/4S
+5
S0
S31
S0
S31
PAC#2
P/S
SMX #2
CM - 1
D12
D0-D9
D11
D10
ODE
Mx
My
Mz
FP
CK
+5
+5
C16
MPU Interface
NOTE:
Connect all inputs not shown to V
SS
10
CONNECTION
MEMORY
DATA
MEMORY
D
D
R
C
A
C
D
From Timing Source
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