參數(shù)資料
型號(hào)： MT9085B
廠商： Mitel Networks Corporation
英文描述： PAC - Parallel Access Circuit(并行存取電路)
中文描述： 委員會(huì)-并行訪問(wèn)電路（并行存取電路）
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 111K
代理商： MT9085B
MT9085B
2-130
Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1)
C16i
CKD=0
Serial
Output
S0-S31
Parallel
Input
MCB=0
OE
Parallel
Input
MCB=1
OE
CKD=1
Serial
Output
S0-S31
Parallel
Input
MCB=0
OE
Parallel
Input
MCB=1
OE
Ch. 31, Bit 0
Ch. 1, Bit 7
Ch. 1, Bit 7
C
1
S
1
C
1
S
2
C
1
S
3
C
1
S
0
C
0
S
31
C
1
S
1
C
1
S
2
C
1
S
3
C
1
S
0
C
0
S
31
C
2
S
0
C
2
S
0
C
1
S
1
C
1
S
2
C
1
S
0
C
1
S
1
C
1
S
2
C
1
S
0
C
0
S
31
C
2
S
0
C
2
S
0
C
2
S
1
C
2
Frame Boundary established by F0i
64 Cycles
Notes:
C
X
S
Y
- on the parallel inputs indicates data closed in with the edge shown will be clocked out on Serial Stream Y, Channel X.
Arrows in the row marked OE indicate the clock edge which latches in the state of the OE pin. C
X
S
Y
written below the arrow indicates the
serial output channel affected by the OE signal. For example, the level on OE clocked in with edge marked C
1
S
1
will enable or disable the
serial output drivers for stream 1 during channel 1.
C
1
S
3
C
1
S
3
C
0
S
31
Ch. 0, Bit 7
C
2
S
1
C
1
S
1
Ch. 31, Bit 0
C
1
S
4
C
1
S
2
C
1
S
3
Ch. 0, Bit 7
C
1
S
1
C
1
S
4
C
1
S
2
C
1
S
3
C
1
S
1
C
1
S
4
C
1
S
2
C
1
S
3
C
2
S
1
C
2
S
1
C
1
S
1
C
1
S
2
C
1
S
3
C
1
S
4
C
2
S
1
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