參數(shù)資料
型號(hào): MT9092
廠商: Mitel Networks Corporation
英文描述: ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II)
中文描述: ISO2 -意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字與HDLC的電話(HPhone -Ⅱ)
文件頁(yè)數(shù): 2/42頁(yè)
文件大小: 482K
代理商: MT9092
MT9092
7-4
Figure 2 - Pin Connections
Pin Description
Pin
#
Name
Description
1
M+
Non-Inverting Microphone (Input).
Non-inverting input to microphone amplifier from the
handset microphone.
2
NC
No Connect.
No internal connection to this pin.
3
V
Bias
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1 μF capacitor to V
SSA
.
Reference voltage for codec (Output).
Nominally [(V
DD
/2)-1.5] volts. Used internally.
Connect 0.1 μF capacitor to V
SSA
.
Internal Connection.
Tie externally to V
SS
for normal operation.
PWRST
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
4
V
Ref
5
IC
6
7
DSTi
ST-BUS Serial Stream (Input).
2048 kbit/s input stream composed of 32 eight bit channels;
the first four of which are used by the MT9092. Input level is TTL compatible.
8
DSTo
ST-BUS Serial Stream (Output).
2048 kbit/s output stream composed of 32 eight bit
channels. The MT9092 sources digital signals during the appropriate channel, time coincident
with the channels used for DSTi.
9
C4i
4096 kHz Clock (Input).
CMOS level compatible.
10
F0i
Frame Pulse (Input).
CMOS level compatible. This input is the frame synchronization pulse
for the 2048 kbit/s ST-BUS stream.
11
V
SSD
IRQ
Digital Ground .
Nominally 0 volts.
12
Interrupt Request (Open Drain Output).
An active low output indicating an unmasked HDLC
interrupt event. Requires 1 k
pull-up to V
DD
.
Serial Port Synchronous Clock (Input).
Data clock for MCS-51 compatible microport. TTL
level compatible.
13
SCLK
1
6
5
4
3
2
4
4
4
4
4
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
2
1
1
2
2
2
2
2
2
2
2
P
I
V
V
N
M
V
M
M
M
DSTi
DSTo
C4i
F0i
VSSD
IRQ
SCLK
DATA 2
DATA 1
CS
WD
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
BP
S12
S11
S10
S9
S8
I
N
N
V
S
S
S
S
S
S
S
44 PIN PLCC
V
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