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MT9092
7-22
Register Summary
This section contains a complete listing of the
HPhone-
II
register addresses, the control/status bit
mapping associated with each register and a
definition of the function of each control/status bit.
The Register Summary may be used for future
reference to review each of the control/status bit
definitions without the need to locate them in the text
of the functional block descriptions.
Adr 16-11
A six bit mask used to interrogate the first byte of the received address. Adr16 is MSB. In the Q.921 specification these
bits are defined to be Sapi5-0.
This bit is used in address comparison if a seven bit address is being checked for (Control bit Seven of Control Register 2
is set). In the Q.921 specification this bit is defined to be C/R (Command/Response).
When this bit is high, this six (or seven) bit mask is used in address comparison of the first address byte. If address
recognition is enabled, any packet failing the address comparison will not be stored in the RX FIFO. A1EN must be high
for All-call (1111111) address recognition for single byte address. When this bit is low, this bit mask is ignored in address
comparison.
Adr 10
A1EN
HDLC Address Recognition Register 1
ADDRESS = 00h WRITE/READ VERIFY
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
Adr16
Adr15
Adr14
Adr13
Adr11
Adr10
A1EN
Adr12
Adr 26-20
A seven bit mask used to interrogate the second byte of the received address. Adr26 is MSB. This mask is ignored (as well
as first byte mask) if an All call address (1111111) is received. In the Q.921 specification these bits are defined to be
Tei6-0.
When this bit is high this seven bit mask is used in address comparison of the second address byte. If address recognition
is enabled, any packet failing the address comparison will not be stored in the RX FIFO. A2EN must be high for All-call
address recognition. When this bit is low, this bit mask is ignored in address comparison.
A2EN
HDLC Address Recognition Register 2
ADDRESS = 01h WRITE/READ VERIFY
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
Adr26
Adr25
Adr24
Adr23
Adr21
Adr20
A2EN
Adr22
The Transmitter FIFO is 19 words deep. Each word consists of 8 bits of data from the internal data bus and 2 status bits from CON-
TROL Register 1 (EOP and FA). If there is data in the Tx FIFO then the lowest data byte in it is loaded into an output shift register for
transmission, and the remaining data shifts down by one word position (Tx FIFO read). A write to a full Tx FIFO will update the top byte
only.
The receiver FIFO is 19 words deep. During a receiver write, the last 8 bits of a shift register buffer and two status bits are loaded into
HDLC Transmit/Receive FIFO Register
ADDRESS = 02h WRITE/READ
Power Reset Value
Not Applicable
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D2
D1
D0
D3