參數(shù)資料
型號: MT9123AP
廠商: Mitel Networks Corporation
英文描述: CMOS Dual Voice Echo Canceller
中文描述: CMOS雙語音回聲消除器
文件頁數(shù): 1/32頁
文件大?。?/td> 191K
代理商: MT9123AP
8-45
Description
The MT9123 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation
conforming
requirements. The MT9123 architecture contains two
echo cancellers which can be configured to provide
dual channel 64 millisecond echo cancellation or
single channel 128 millisecond echo cancellation.
to
ITU-T
G.165
The MT9123 operates in two major modes:
Controller or Controllerless. Controller mode allows
access to an array of features for customizing the
MT9123 operation. Controllerless mode is for
applications where default register settings are
sufficient.
Features
Dual channel 64ms or single channel 128ms
echo cancellation
Conforms to ITU-T G.165 requirements
Narrow-band signal detection
Programmable double-talk detection threshold
Non-linear processor with adaptive suppression
threshold and comfort noise insertion
Offset nulling of all PCM channels
Controllerless mode or Controller mode with
serial interface
ST-BUS or variable-rate SSI PCM interfaces
Selectable
μ
/A-Law ITU-T G.711;
μ
/A-Law Sign
Mag; linear 2’s complement
Per channel selectable 12 dB attenuator
Transparent data transfer and mute option
19.2 MHz master clock operation
Applications
Wireless Telephony
Trunk echo cancellers
Figure 1 - Functional Block Diagram
Linear/
μ
/A-Law
+
Non-Linear
Processor
Offset
Null
Linear/
μ
/A-Law
Linear/
μ
/A-Law
Microprocessor
Interface
Double-Talk
Detector
A
F
C
Narrow-Band
Detector
Linear/
μ
/A-Law
Offset
Null
12dB
Attenuator
Echo Canceller A
Echo Canceller B
VDD
VSS
PWRDN
IC1
F0od
F0i
BCLK/C4i
MCLK
Sout
Rin
ENA1
ENB1
CONFIG1
CONFIG2
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK
Sin
Rout
ENA2
ENB2
NLP
LAW
FORMAT
IC3
IC4
-
Programmable
Bypass
IC2
ISSUE 1
October 1996
Ordering Information
MT9123AP
MT9123AE
-40
°
C to + 85
°
C
28 Pin PLCC
28 Pin PDIP
MT9123
Dual Voice Echo Canceller
Preliminary Information
CMOS
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