參數(shù)資料
型號: MT9123AP
廠商: Mitel Networks Corporation
英文描述: CMOS Dual Voice Echo Canceller
中文描述: CMOS雙語音回聲消除器
文件頁數(shù): 2/32頁
文件大?。?/td> 191K
代理商: MT9123AP
MT9123
Preliminary Information
8-46
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
ENA1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input)
. This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for Echo Canceller A
on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
2
ENB1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input)
. This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
3
ENA2
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input)
. This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller A on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
S2/DATA2
S3/CS
VDD
F0od
S1/DATA1
IC4
IC3
S4/SCLK
Sout
Rout
BCLK/C4i
F0i
CONFIG1
CONFIG2
Sin
VSS
MCLK
IC1
Rin
NLP
IC2
LAW
ENB2
ENB1
ENA2
FORMAT
PWRDN
ENA1
E
E
E
E
B
C
C
Sin
VSS
MCLK
IC1
Rin
NLP
IC2
F
L
P
I
I
S
S
S2/DATA2
VDD
F0od
S1/DATA1
Sout
Rout
F0i
PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3
2
1
2
2
2
1
1
1
1
1
1
1
PDIP
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