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Preliminary Information
MT9126
8-43
Figure 7 - ST-BUS 8-bit Companded PCM Relative Timing
MCLK (C4)
F0i
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ADPCMi
ADPCMo
C2o (output)
B1
B2
B3
B4
EN1 (output)
EN2 (output)
PCMi2
PCMo2
B3
B4
PCMi1
PCMo1
B1
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D
C
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B1
SEL=0
SEL=1
B2
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32 kb/s is shown
In 24 kb/s, bit 4 becomes “X”
16 kb/s
SEL operates for
16 kb/s only
ENB2/F0od
7 6 5 4
7 6 5 4 3 2 1 0
3 2 1 0
7 6 5 4
7 6 5 4 3 2 1 0
3 2 1 0
7 6 5 4
7 6 5 4 3 2 1 0
3 2 1 0
0 1
7 6 5 4 3 2 1 0
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 3 4
1 2 3 4 1 2 3 4
1 2 3 4
7 6 5 4
7 6 5 4 3 2 1 0
3 2 1 0
0 1
7 6 5 4 3 2 1 0
transparent relay of D- and C- channels
when ENB1=0
0 1
7 6 5 4 3 2 1 0
1 2 3 4
1 2 3 4 1 2 3 4
1 2 3 4
0 1
7 6 5 4 3 2 1 0
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X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
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outputs=High impedance
inputs = don’t care
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Two frame delay from data input to data output