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參數(shù)資料
| 型號(hào)： | MT9196 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Phone Circuit (IDPC)(集成數(shù)字電話電路) |
| 中文描述： | 綜合數(shù)字電話電路（前列腺偶發(fā)癌）（集成數(shù)字電話電路） |
| 文件頁(yè)數(shù)： | 34/43頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | MT9196 |
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MT9196
7-168
Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC and A/
μ
and refer to Control Register 2, address 0Fh.
AC Electrical Characteristics
- ST-BUS Timing (See Figure 12)
Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions
→
data-data, data-HiZ, HiZ-data.
Figure 12 - ST-BUS Timing Diagram
Electrical Characteristics
for Analog Inputs
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Input voltage without overloading
CODEC
at MIC+
at AUXin
across M+/M-
V
IOLM
V
IOLA
V
IOLH
1.63
0.580
1.63
0.580
2.90
1.03
Vp-p
Vp-p
Vp-p
Vp-p
Vp-p
Vp-p
TxINC = 0, A/
μ
= 0*
TxINC = 1, A/
μ
= 1*
TxINC = 1, A/
μ
= 0*
TxINC = 1, A/
μ
= 1*
TxINC = 0, A/
μ
= 0*
TxINC = 1, A/
μ
= 1*
Tx filter gain=0dB setting
M+/M-, MIC+
AUXin
to V
SS
2
Input impedance
Z
I
Z
IA
50
10
k
k
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
C4i Clock Period
C4i Clock High period
C4i Clock Low period
C4i Clock Transition Time
F0i Frame Pulse Setup Time
F0i Frame Pulse Hold Time
DSTo Delay
DSTi Setup Time
DSTi Hold Time
t
C4P
t
C4H
t
C4L
t
T
t
F0iS
t
F0iH
t
DSToD
t
DSTiS
t
DSTiH
244
122
122
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
100
125
C
L
= 50pF, 1k
load.*
30
30
DSTo
DSTi
70%
30%
70%
30%
70%
30%
70%
30%
NOTE:
Levels refer to %V
DD
t
T
t
T
t
C4L
t
C4H
t
C4P
1 bit cell
t
DSTiS
t
DSTiH
t
F0iS
t
F0iH
t
T
t
DSToD
t
T
C4i
F0i
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