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參數(shù)資料
| 型號： | MT91L61AS |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | ISO2-CMOS 3 Volt Multi-Featured Codec (MFC) |
| 中文描述： | ISO2 - CMOS三伏多功能的編解碼器（MFC）中 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大小： | 146K |
| 代理商： | MT91L61AS |
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Advance Information
MT91L60/61
7
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
the
reference
frame,
microprocessor D-Channel read and write operations
are performed, then:
during
which
the
Figure 4 - Serial Port Relative Timing for Intel Mode 0
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
X
X
A
2
A
1
A
0
R/W
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Delays due to internal processor timing which are transparent.
The MT91L60/L61:latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
y
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
y
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
D
7
D
0
X
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
y
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
R/W
X
A
1
A
0
X
D
7
D
0
Delays due to internal processor timing which are transparent .
The MT91L60/L61: latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
y
X
X
A
2
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT91L61ASR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3 Volt Multi-Featured Codec (MFC) |
| MT91L61ASR1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3 Volt Multi-Featured Codec (MFC) |
| MT91L62 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3 Volt Single Rail Codec |
| MT91L62AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 3 Volt Single Rail Codec |
| MT91L62AN | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3 Volt Single Rail Codec |
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