參數(shù)資料
型號(hào): MT9300BL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Multi-Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP160
封裝: MQFP-160
文件頁(yè)數(shù): 26/39頁(yè)
文件大小: 629K
代理商: MT9300BL
MT9300B
Data Sheet
26
Zarlink Semiconductor Inc.
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
15
EP
14
EP
13
EP
12
EP
10
EP
9
EP
8
EP
11
Echo Canceller A, Error Peak Detect Register 2 (EP)
Echo Canceller B, Error Peak Detect Register 2 (EP)
Read Address: 11
H
+ Base Address
Read Address: 31
H
+ Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
7
EP
6
EP
5
EP
4
EP
2
EP
1
EP
0
EP
3
Echo Canceller A, Error Peak Detect Register 1 (EP)
Echo Canceller B, Error Peak Detect Register 1 (EP)
Read Address: 10
H
+ Base Address
Read Address: 30
H
+ Base Address
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement linear coded
format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.
Power Reset Value
48H
7
6
5
4
3
2
1
0
DTDT
15
DTDT
14
DTDT
13
DTDT
12
DTDT
10
DTDT
9
DTDT
8
DTDT
11
Echo Canceller A, Double-Talk Detection Threshold Register 2
Echo Canceller B, Double-Talk Detection Threshold Register 2
Read/Write Address: 15
H
+ Base Address
Read/Write Address: 35
H
+ Base Address
Power Reset Value
00H
7
6
5
4
3
2
1
0
DTDT
7
DTDT
6
DTDT
5
DTDT
4
DTDT
2
DTDT
1
DTDT
0
DTDT
3
Echo Canceller A, Double-Talk Detection Threshold Register 1
Echo Canceller B, Double-Talk Detection Threshold Register 1
Read/Write Address: 14h + Base Address
Read/Write Address: 34h + Base Address
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value
defaults
to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in
Register 1.
(DTDT)
(DTDT)
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