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參數(shù)資料
| 型號： | MT9300BV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Multi-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件頁數(shù)： | 28/39頁 |
| 文件大?。?/td> | 629K |
| 代理商： | MT9300BV |
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MT9300B
Data Sheet
28
Zarlink Semiconductor Inc.
Bit
Name
Description
7
WR_all
Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped
into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16
Groups of Echo Cancellers as per Group 0.
When low, address mapping is per Figure 8.
Note:
Only the
Main Control Register 0
has the WR_all bit.
6
ODE
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When
both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are
high impedance
.
Note:
Only the
Main Control Register 0
has the ODE bit.
5
MIRQ
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are
masked. The Tone Detectors operate as specified in their Echo Canceller B, Control
Register 2.
When low, the Tone Detectors Interrupts are active.
Note:
Only the
Main Control Register 0
has the MIRQ bit.
4
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller B is masked. The Tone Detector operates as specified in Echo
Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
3
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller A is masked. The Tone Detector operates as specified in Echo
Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
2
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept
ITU-T (G.711) PCM code.
When low, both Echo Cancellers A and B for a given group, accept sign-magnitude
PCM code
.
1
LAW
A/m Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code.
When low, both Echo Cancellers A and B for a given group, accept m-Law companded
PCM code.
Main Control Register 0
(EC group 0)
Read/Write Address:
400
H
PWUP
LAW
Format
MTDAI
MTDBI
MIRQ
ODE
WR_all
7
6
5
4
3
2
1
0
Reset Value:
00
H
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT933 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
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