參數(shù)資料
型號(hào)： MT9300BV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： Multi-Channel Voice Echo Canceller
中文描述： DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝： 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁(yè)數(shù)： 36/39頁(yè)
文件大?。?/td> 629K
代理商： MT9300BV
MT9300B
Data Sheet
36
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25
°
C, V
DD1
=3.3 V and for design aid only: not guaranteed and not subject to production testing
Figure 13 - Master Clock
Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25
°
C, V
DD1
=3.3 V and for design aid only: not guaranteed and not subject to production testing
* Note 1:High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
AC Electrical Characteristics
- Master Clock
- Voltages are with respect to ground (V
SS
). unless otherwise stated.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
Master Clock Frequency,
- Fsel = 0
- Fsel = 1
Master Clock Low
Master Clock High
f
MCF0
f
MCF1
19.0
9.5
20
20
20.0
10.0
21.0
10.5
MHz
MHz
ns
ns
2
3
t
MCL
t
MCH
AC Electrical Characteristics
- Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
6
7
8
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data delay on read
Data hold on read
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
DDR
t
DHR
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
79
15
C
L
=150pF, R
L
=1K
C
L
=150pF, R
L
=1K
See Note 1
3
9
10
11
12
Data setup on write
Data hold on write
Acknowledgment delay
Acknowledgment hold time
t
DSW
t
DHW
t
AKD
t
AKH
0
0
ns
ns
ns
ns
80
8
C
L
=150pF, R
L
=1K
C
L
=150pF, R
L
=1K,
See Note 1
C
L
=150pF, R
L
=1K,
See Note 1
0
13
IRQ delay
t
IRD
20
65
ns
t
MCH
t
MCL
V
TT
MCLK
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